Patents by Inventor Chun-Pei Wu

Chun-Pei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100006974
    Abstract: The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings.
    Type: Application
    Filed: July 14, 2008
    Publication date: January 14, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jeff J. Xu, Chia-Ta Hsieh, Chun-Pei Wu, Chun-Hung Lee
  • Patent number: 7619277
    Abstract: A flash memory includes substrate, control gates, trenches, source regions, isolation structures, drain regions, a common source line, floating gates, tunneling dielectric layers, and dielectric layer. The control gates and the trenches are in first and second directions on the substrate, respectively. The source regions are in the substrate and trenches on one side of control gates. The isolation structures fill the trenches between the source regions. The drain regions are in the substrate on the other side of control gates between the isolation structures. The common source line is in the second direction inside the substrate and electrically connected to the source regions. Furthermore, the floating gates are between the control gates and the substrate that between the source and drain regions. The tunneling dielectric layers are disposed between the floating gates and the substrate, and the dielectric layer is disposed between the floating and control gates.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: November 17, 2009
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chun-Pei Wu, Huei-Huang Chen, Wen-Bin Tsai
  • Patent number: 7384848
    Abstract: A method for forming a non-volatile memory with inlaid floating gate is disclosed. The method comprises the following steps. A substrate having a pad dielectric layer and a first dielectric layer thereon is provided. Then a buried diffusion region is formed in the substrate. Next a second dielectric layer is formed over the substrate and the second dielectric layer and the pad dielectric layer are then etched back to expose the buried diffusion region and the first dielectric layer. Then a shallow trench isolation is formed into the expose the buried diffusion region and the substrate. Next a floating gate pattern is transferred into the first and second dielectric layers. Next the first dielectric layer is removed to expose the pad dielectric layer. Then the exposed pad dielectric layer is removed to expose the substrate. Next a tunnel dielectric layer is formed on the exposed substrate.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: June 10, 2008
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Pei Wu, Wei-Ming Chung, Huei-Huarng Chen
  • Patent number: 7354824
    Abstract: A method for fabricating a non-volatile memory is provided. A dielectric layer, a first conductive layer, and a mask layer are formed sequentially on a substrate and then patterned to form a number of openings and floating gates. In addition, spacers are formed on the sidewalls of the openings. A source/drain region is formed in the substrate underneath each of the openings. A thermal process is performed to oxidize the substrate exposed by the opening to form an insulating layer above the source/drain region. Afterward, the mask layer is removed and an inter-gate dielectric layer is formed to cover the surface of the first conductive layer and the surface of the insulating layer. Subsequently, a second conductive layer is formed on the inter-gate dielectric layer.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: April 8, 2008
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Hsin-Fu Lin, Chun-Pei Wu
  • Publication number: 20080026527
    Abstract: A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Applicant: Macronix International Co., Ltd.
    Inventors: Kuan Fu Chen, Yin Jen Chen, Meng Hsuan Weng, Tzung Ting Han, Ming Shang Chen, Chun Pei Wu
  • Publication number: 20080020525
    Abstract: A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.
    Type: Application
    Filed: July 24, 2006
    Publication date: January 24, 2008
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Yuan Lo, Chun-Pei Wu
  • Publication number: 20070284644
    Abstract: A method for fabricating a floating gate memory device comprises using thin buried diffusion regions with increased encroachment by a buried diffusion oxide layer into the buried diffusion layer and underneath the tunnel oxide under the floating gate. Further, the floating gate polysilicon layer has a eight than the buried diffusion height. The increased step height of the gate polysilicon layer to the buried diffusion layer, and the increased encroachment of the buried diffusion oxide, can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.
    Type: Application
    Filed: June 13, 2006
    Publication date: December 13, 2007
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chen-Chin Liu, Chun-Pei Wu, Ta-Kang Chu, Yao-Fu Chan
  • Patent number: 7307296
    Abstract: A flash memory comprises a substrate, control gates, doped regions, an isolation layer, isolation structures, floating gates, tunneling dielectric layers and inter-gate dielectric layers. The control gates are arranged over the substrate with a first direction, and the doped regions are arranged within the substrate with a second direction. The isolation layers are disposed between the control gates and the doping regions, and the isolation structures are disposed within the substrate where the doped regions and the control gates do not overlap. Furthermore, the floating gates are disposed between the control gates and the substrate that is not covered by the isolation layers. The tunneling dielectric layers are disposed between the substrate and the floating gates. The inter-gate dielectric layers are disposed between the control gates and the floating gates.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: December 11, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Fu Lin, Chun-Pei Wu
  • Publication number: 20070264774
    Abstract: A method of manufacturing a flash memory device having an enhanced gate coupling ratio includes steps of forming a first semiconductor layer on a substrate and forming a semiconductor spacer layer on top of the first semiconductor layer. The semiconductor spacer layer includes a plurality of recesses. The method provides a semiconductor spacer structure which functions to increase the contact area between a floating gate and a control gate of the flash memory device.
    Type: Application
    Filed: May 12, 2006
    Publication date: November 15, 2007
    Applicant: Macronix International Co., Ltd.
    Inventors: Tian-Shuan Luo, Chun-Pei Wu
  • Publication number: 20070259496
    Abstract: A method for fabricating a non-volatile memory is provided. A dielectric layer, a first conductive layer, and a mask layer are formed sequentially on a substrate and then patterned to form a number of openings and floating gates. In addition, spacers are formed on the sidewalls of the openings. A source/drain region is formed in the substrate underneath each of the openings. A thermal process is performed to oxidize the substrate exposed by the opening to form an insulating layer above the source/drain region. Afterward, the mask layer is removed and an inter-gate dielectric layer is formed to cover the surface of the first conductive layer and the surface of the insulating layer. Subsequently, a second conductive layer is formed on the inter-gate dielectric layer.
    Type: Application
    Filed: May 3, 2006
    Publication date: November 8, 2007
    Inventors: Hsin-Fu Lin, Chun-Pei Wu
  • Publication number: 20070117301
    Abstract: A method for forming a non-volatile memory with inlaid floating gate is disclosed. The method comprises the following steps. A substrate having a pad dielectric layer and a first dielectric layer thereon is provided. Then a buried diffusion region is formed in the substrate. Next a second dielectric layer is formed over the substrate and the second dielectric layer and the pad dielectric layer are then etched back to expose the buried diffusion region and the first dielectric layer. Then a shallow trench isolation is formed into the expose the buried diffusion region and the substrate. Next a floating gate pattern is transferred into the first and second dielectric layers. Next the first dielectric layer is removed to expose the pad dielectric layer. Then the exposed pad dielectric layer is removed to expose the substrate. Next a tunnel dielectric layer is formed on the exposed substrate.
    Type: Application
    Filed: November 18, 2005
    Publication date: May 24, 2007
    Applicant: Macronix International Co., Ltd.
    Inventors: Chun-Pei Wu, Wei-Ming Chung, Huei-Huarng Chen
  • Publication number: 20060284267
    Abstract: A flash memory comprises a substrate, control gates, doped regions, an isolation layer, isolation structures, floating gates, tunneling dielectric layers and inter-gate dielectric layers. The control gates are arranged over the substrate with a first direction, and the doped regions are arranged within the substrate with a second direction. The isolation layers are disposed between the control gates and the doping regions, and the isolation structures are disposed within the substrate where the doped regions and the control gates do not overlap. Furthermore, the floating gates are disposed between the control gates and the substrate that is not covered by the isolation layers. The tunneling dielectric layers are disposed between the substrate and the floating gates. The inter-gate dielectric layers are disposed between the control gates and the floating gates.
    Type: Application
    Filed: June 20, 2005
    Publication date: December 21, 2006
    Inventors: Hsin-Fu Lin, Chun-Pei Wu
  • Publication number: 20060286746
    Abstract: A flash memory includes substrate, control gates, trenches, source regions, isolation structures, drain regions, a common source line, floating gates, tunneling dielectric layers, and dielectric layer. The control gates and the trenches are in first and second directions on the substrate, respectively. The source regions are in the substrate and trenches on one side of control gates. The isolation structures fill the trenches between the source regions. The drain regions are in the substrate on the other side of control gates between the isolation structures. The common source line is in the second direction inside the substrate and electrically connected to the source regions. Furthermore, the floating gates are between the control gates and the substrate that between the source and drain regions. The tunneling dielectric layers are disposed between the floating gates and the substrate, and the dielectric layer is disposed between the floating and control gates.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 21, 2006
    Inventors: Chun-Pei Wu, Huei-Huang Chen, Wen-Bin Tsai
  • Patent number: 6979620
    Abstract: A method for fabricating a flash memory cell is provided. After an ONO dielectric layer is formed on a first conductive layer over a tunnel oxide layer, a second conductive layer is formed on the ONO dielectric layer. Then, patterning the second conductive layer to form a periphery region comprising an exposed portion of a semiconductor substrate and a memory cell region comprising the left second conductive layer. During the present process, the ONO dielectric layer is protected from being exposed in various solvents and gases with the second conductive layer. Thus, a flash memory cell with a high-quality ONO gate dielectric layer, without increasing complexity of the process and additional masks, is obtained.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: December 27, 2005
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Pei Wu, Huei-Huarng Chen, Hong-Chi Chen, Hsuan-Ling Kao
  • Patent number: 6821841
    Abstract: A method for fabricating a mask read-only-memory with diode cells is provided. A doped conductive layer with a first conductivity is formed on bit lines. Then, a photoresist layer with a mask ROM pattern is formed on an interlayer dielectric layer on the doped conductive layer for serving as an etching mask, thereby forming openings in the interlayer dielectric layer unto the exposed regions of the doped conductive layer. Performing ion implantation to form a diffusion region with a second conductivity opposite to the first conductivity in each exposed region of the doped conductive layer, so that the doped conductive layer and the diffusion regions formed therein constitute diode cells that are served as memory cells. A contact plug is formed in each opening unto the diode cell and a conductive layer is formed on the contact plug for serving as word lines.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: November 23, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Pei Wu, Huei-Huarng Chen, Wen-Bin Tsai, Hsuan-Ling Kao
  • Patent number: 6787056
    Abstract: A planarization method using anisotropic etching can be applied to planarize an insulating layer with an uneven surface on a substrate. H2SO4, H3PO4, HF and H2O are mixed to form an etching solution. The substrate is placed into the etching solution to make the etching solution pass the surface of the insulating layer at a flow rate to etch the insulating layer. After a period of etching time, the insulating layer with a more planar surface can be obtained.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: September 7, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Wen-Bin Tsai, Ching-Yu Chang, Chun-Pei Wu, Huei-Huang Chen, Samuel C. Pan
  • Publication number: 20040079984
    Abstract: A polysilicon self-alignment contact and a polysilicon common source line. A cell array formed on a semiconductor substrate has a second cell adjacent to a first cell in a Y-axis orientation, and a third cell adjacent to the first cell in an X-axis orientation. Each cell comprises a first gate structure and a second gate structure, a source region formed in the semiconductor substrate adjacent to the first gate structure and the second gate structure, and an opening formed between the first gate structure and the second gate structure to expose the source region. A drain region is formed in the semiconductor substrate adjacent to the second gate structure of the first cell and the first gate structure of the second cell. A contact hole is formed between the first cell and the second cell to expose the drain region. A polysilicon layer is formed in the contact hole to serve as a polysilicon self-aligned contact.
    Type: Application
    Filed: October 25, 2002
    Publication date: April 29, 2004
    Inventors: Hsuan-Ling Kao, Chun-Pei Wu, Hui-Huang Chen, Wen-Bin Tsai, Henry Chung
  • Publication number: 20030146190
    Abstract: A planarization method using anisotropic etching can be applied to planarize an insulating layer with an uneven surface on a substrate. H2SO4, H3PO4, HF and H2O are mixed to form an etching solution. The substrate is placed into the etching solution to make the etching solution pass the surface of the insulating layer at a flow rate to etch the insulating layer. After a period of etching time, the insulating layer with a more planar surface can be obtained.
    Type: Application
    Filed: February 7, 2002
    Publication date: August 7, 2003
    Inventors: Wen-Bin Tsai, Ching-Yu Chang, Chun-Pei Wu, Huei-Huang Chen, Samuel C. Pan
  • Patent number: 6495430
    Abstract: A process for fabricating a sharp corner-free shallow trench isolation structure. First, a SiON layer and a mask layer are successively formed on a semiconductor substrate. The SiON layer and mask layer are patterned to form an opening, exposing the substrate region on which a shallow trench isolation region will be formed. Next, an oxide spacer is formed on sidewalls of the SiON layer and mask layer. A trench is formed in the semiconductor substrate using the spacer and mask layer as a mask. Next, a liner oxide layer is formed on the surface of the trench by thermal oxidation, such that the liner oxide layer near the SiON layer is in a bird's beak form. An isolating oxide layer is filled in the trench. Finally, the mask layer and SiON layer are removed. The present invention forms a short and thick bird's beak structure and rounded trench corner. Therefore, the thickness of the tunnel oxide is even and the tunnel oxide integrity remains.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: December 17, 2002
    Assignee: Macronix International Co., Ltd.
    Inventors: Wen-Bin Tsai, Chun-Pei Wu, Hui-Huang Chen