Patents by Inventor Chun-Ren Cheng
Chun-Ren Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12377441Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a dielectric stack disposed on a substrate. The integrated chip structure further includes one or more piezoelectric ultrasonic transducers (PMUTs) and one or more capacitive ultrasonic transducers (CMUTs). The one or more PMUTs include a piezoelectric stack disposed within the dielectric stack over one or more PMUT cavities. The one or more CMUTs include electrodes disposed within the dielectric stack and separated by one or more CMUT cavities. An isolation chamber is arranged within the dielectric stack laterally between the one or more PMUTs and the one or more CMUTs. The isolation chamber vertically extends past at least a part of both the one or more PMUTs and the one or more CMUTs.Type: GrantFiled: June 6, 2022Date of Patent: August 5, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Hui Lin, Yi-Hsien Chang, Chun-Ren Cheng, Fu-Chun Huang, Yi Heng Tsai, Shih-Fen Huang, Chao-Hung Chu, Po-Chen Yeh
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Publication number: 20250244284Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.Type: ApplicationFiled: January 18, 2025Publication date: July 31, 2025Applicant: Tawian Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Cheng HUANG, Yi-Hsien Chang, Chin-Hua Wen, Chun-Ren Cheng, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Ching-Hui Lin, Sean Cheng, Hector Chang
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Patent number: 12361745Abstract: The structure of a semiconductor device with an array of bioFET sensors, a biometric fingerprint sensor, and a temperature sensor and a method of fabricating the semiconductor device are disclosed. A method for fabricating the semiconductor device includes forming a gate electrode on a first side of a semiconductor substrate, forming a channel region between source and drain regions within the semiconductor substrate, and forming a piezoelectric sensor region on a second side of the semiconductor substrate. The second side is substantially parallel and opposite to the first side. The method further includes forming a temperature sensing electrode on the second side during the forming of the piezoelectric sensor region, forming a sensing well on the channel region, and binding capture reagents on the sensing well.Type: GrantFiled: April 19, 2021Date of Patent: July 15, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Fu-Chun Huang
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Patent number: 12364162Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.Type: GrantFiled: May 31, 2024Date of Patent: July 15, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Fu-Chun Huang
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Publication number: 20250207687Abstract: Various embodiments of the present disclosure are directed to a normally-open piezoelectric microelectromechanical systems (MEMS) device. A cantilever has a first end overlying and bonded to a substrate and further has a second end, opposite the first end, overlying an actuator cavity. A piezoelectric actuator is on the cantilever. A valve vane is bonded to the second end of the cantilever and further overlies a valve cavity laterally adjacent to the actuator cavity. The cantilever curves downward from the first end to the second end, such that the valve vane is inclined and the valve cavity is open. Actuation of the piezoelectric actuator curves the cantilever upward to close the valve cavity.Type: ApplicationFiled: March 27, 2024Publication date: June 26, 2025Inventors: Yi-Hsien Chang, Fu-Chun Huang, Po-Chen Yeh, Ching-Hui Lin, Chao-Hung Chu, Chun-Ren Cheng, Shih-Fen Huang
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Patent number: 12326416Abstract: A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.Type: GrantFiled: April 10, 2023Date of Patent: June 10, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Fu-Chun Huang
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Patent number: 12297105Abstract: A method of fabricating a semiconductor structure includes: providing a first wafer; providing a second wafer having a first surface and a second surface opposite to the first surface; contacting the first surface of the second wafer with the first wafer; and forming a plurality of scribe lines on the second surface of the second wafer, wherein the formation of the plurality of scribe lines includes removing portions of the second wafer from the second surface towards the first surface to form a third surface between the first surface and the second surface, and the plurality of scribe lines protrudes from the third surface of the second wafer.Type: GrantFiled: July 27, 2023Date of Patent: May 13, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Cheng Shen, Yi-Hsien Chang, Yi-Heng Tsai, Chun-Ren Cheng
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Publication number: 20250145454Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.Type: ApplicationFiled: January 6, 2025Publication date: May 8, 2025Inventors: PO CHEN YEH, YI-HSIEN CHANG, FU-CHUN HUANG, CHING-HUI LIN, CHIAHUNG LIU, SHIH-FEN HUANG, CHUN-REN CHENG
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Publication number: 20250122071Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity.Type: ApplicationFiled: December 27, 2024Publication date: April 17, 2025Inventors: Fan Hu, Chun-Ren Cheng, Hsiang-Fu Chen, Wen-Chuan Tai
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Patent number: 12264362Abstract: An integrated semiconductor device for manipulating and processing bio-entity samples and methods are described. The device includes a lower substrate, at least one optical signal conduit disposed on the lower substrate, at least one cap bonding pad disposed on the lower substrate, a cap configured to form a capped area, and disposed on the at least one cap bonding pad, a fluidic channel, wherein a first side of the fluidic channel is formed on the lower substrate and a second side of the fluidic channel is formed on the cap, a photosensor array coupled to sensor control circuitry, and logic circuitry coupled to the fluidic control circuitry, and the sensor control circuitry.Type: GrantFiled: July 17, 2023Date of Patent: April 1, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Allen Timothy Chang, Yi-Hsien Chang, Chun-Ren Cheng
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Patent number: 12227410Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.Type: GrantFiled: January 5, 2024Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Po Chen Yeh, Yi-Hsien Chang, Fu-Chun Huang, Ching-Hui Lin, Chiahung Liu, Shih-Fen Huang, Chun-Ren Cheng
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Publication number: 20250056874Abstract: One aspect of the present disclosure pertains to a device. The device includes a substrate, a logic circuit disposed on the substrate, and a nanoelectromechanical systems (NEMS) device electrically connected to the logic circuit and formed on the substrate. The NEMS device includes a first electrode electrically connected to the logic circuit, a second electrode electrically connected to a first power supply, a movable feature electrically connected to the second electrode, and a control electrode operable to move the movable feature relative to the first electrode.Type: ApplicationFiled: November 17, 2023Publication date: February 13, 2025Inventors: Hung-Li Chiang, Ching-Hui Lin, Chun-Ren Cheng, Iuliana Radu
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Patent number: 12215016Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.Type: GrantFiled: August 7, 2023Date of Patent: February 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fan Hu, Chun-Ren Cheng, Hsiang-Fu Chen, Wen-Chuan Tai
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Publication number: 20240401714Abstract: A piezoelectric valve may be formed using semiconductor processing techniques such that the piezoelectric valve is biased in a normally closed configuration. Actuation of the piezoelectric valve may be achieved through the use of a piezoelectric-based actuation layer of the piezoelectric valve. The piezoelectric valve may be implemented in various use cases, such as a dispensing valve for precise drug delivery, a relief valve to reduce the occlusion effect in speaker-based devices (e.g., in-ear headphones), a pressure control valve, and/or another type of valve that is configured for microfluidic control, among other examples. The normally closed configuration of the piezoelectric valve enables the piezoelectric valve to operate as a normally closed valve with reduced power consumption.Type: ApplicationFiled: August 22, 2023Publication date: December 5, 2024Inventors: Yi-Hsien CHANG, Fu-Chun HUANG, Po-Chen YEH, Chao-Hung CHU, Ching-Hui LIN, Chun-Ren CHENG, Shih-Fen HUANG
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Publication number: 20240393291Abstract: A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Hui Lin, Chun-Ren CHENG, Shih-Fen HUANG, Fu-Chun HUANG
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PIEZOELECTRIC DEVICE HAVING PIEZOELECTRIC STRUCTURE DISPOSED BETWEEN PATTERNED CONDUCTIVE STRUCTURES
Publication number: 20240397828Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric device including a piezoelectric structure over a substrate. A first conductive structure is disposed on a lower surface of the piezoelectric structure. The first conductive structure includes one or more first movable elements directly contacting the piezoelectric structure. A second conductive structure is disposed on an upper surface of the piezoelectric structure. The second conductive structure includes one or more second movable elements directly contacting the piezoelectric structure. The one or more second movable elements directly overlie the one or more first movable elements.Type: ApplicationFiled: May 22, 2023Publication date: November 28, 2024Inventors: Ching-Hui Lin, Yi-Hsien Chang, Chun-Ren Cheng, Shih-Fen Huang, Fu-Chun Huang, Chao-Hung Chu, Po-Chen Yeh -
Publication number: 20240373753Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.Type: ApplicationFiled: July 15, 2024Publication date: November 7, 2024Inventors: Alexander Kalnitsky, Chun-Ren Cheng, Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yan-Jie Liao
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Publication number: 20240324463Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.Type: ApplicationFiled: May 31, 2024Publication date: September 26, 2024Inventors: Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Fu-Chun Huang
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Patent number: 12082505Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.Type: GrantFiled: August 5, 2022Date of Patent: September 3, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Alexander Kalnitsky, Chun-Ren Cheng, Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yan-Jie Liao
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INTEGRATION SCHEME FOR BREAKDOWN VOLTAGE ENHANCEMENT OF A PIEZOELECTRIC METAL-INSULATOR-METAL DEVICE
Publication number: 20240290541Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure and a second conductive structure. A dielectric structure is arranged between the first conductive structure and the second conductive structure. The dielectric structure comprises an upper region over a lower region. The lower region comprises a first lateral surface and a second lateral surface on opposing sides of the upper region. A passivation layer overlies the second conductive structure and the dielectric structure. The passivation layer comprises a lateral segment contacting the first lateral surface. A height of the lateral segment is greater than a height of the upper region. A top surface of the lateral segment is below a top surface of the passivation layer.Type: ApplicationFiled: May 9, 2024Publication date: August 29, 2024Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao