Patents by Inventor Chun-Sheng Chiang

Chun-Sheng Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12166034
    Abstract: A semiconductor device includes a silicon substrate and a fin formed above the substrate. The fin provides active regions for two devices, such as gate-all-around transistors. The semiconductor device also includes a fin-insulating structure positioned to electrically isolate the active regions for the two devices. The fin-insulating structure is formed in a trench, with a first portion adjacent the fin and a second portion below the fin and extending into the substrate. The fin-insulating structure includes an oxide liner in the second portion of the trench, but not the first portion. The fin-insulating structure is further filled with an insulating material such as silicon nitride.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wei Wu, Hsin-Che Chiang, Chun-Sheng Liang, Jeng-Ya Yeh
  • Publication number: 20240385527
    Abstract: A control system includes a plurality of pressure sensors, each to detect a pressure in a respective dynamic gas lock (DGL) nozzle control region of a plurality of DGL nozzle control regions. Each DGL nozzle control region includes one or more DGL nozzles. The control system includes a plurality of mass flow controllers (MFCs). Each MFC of the plurality of MFCs is to control a flow velocity in a respective DGL nozzle control region of the plurality of DGL nozzle control regions. The control system includes a controller to selectively cause one or more MFCs of the plurality of MFCs to adjust flow velocities in one or more DGL nozzle control regions of the plurality of DGL nozzle control regions based on pressures detected by the plurality of pressure sensors in DGL nozzle control regions of the plurality of DGL nozzle control regions.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chun-Kai CHANG, Yu Sheng CHIANG, Yu De LIOU, Chi YANG, Ching-Juinn HUANG, Po-Chung CHENG
  • Publication number: 20240379666
    Abstract: A semiconductor device includes a silicon substrate and a fin formed above the substrate. The fin provides active regions for two devices, such as gate-all-around transistors. The semiconductor device also includes a fin-insulating structure positioned to electrically isolate the active regions for the two devices. The fin-insulating structure is formed in a trench, with a first portion adjacent the fin and a second portion below the fin and extending into the substrate. The fin-insulating structure includes an oxide liner in the second portion of the trench, but not the first portion. The fin-insulating structure is further filled with an insulating material such as silicon nitride.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Chi-Wei Wu, Hsin-Che Chiang, Chun-Sheng Liang, Jeng-Ya Yeh
  • Publication number: 20240363731
    Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Wei-Chih Kao, Hsin-Che Chiang, Yu-San Chien, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 12087844
    Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chih Kao, Hsin-Che Chiang, Yu-San Chien, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 12085861
    Abstract: A control system includes a plurality of pressure sensors, each to detect a pressure in a respective dynamic gas lock (DGL) nozzle control region of a plurality of DGL nozzle control regions. Each DGL nozzle control region includes one or more DGL nozzles. The control system includes a plurality of mass flow controllers (MFCs). Each MFC of the plurality of MFCs is to control a flow velocity in a respective DGL nozzle control region of the plurality of DGL nozzle control regions. The control system includes a controller to selectively cause one or more MFCs of the plurality of MFCs to adjust flow velocities in one or more DGL nozzle control regions of the plurality of DGL nozzle control regions based on pressures detected by the plurality of pressure sensors in DGL nozzle control regions of the plurality of DGL nozzle control regions.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Kai Chang, Yu Sheng Chiang, Yu De Liou, Chi Yang, Ching-Juinn Huang, Po-Chung Cheng
  • Publication number: 20240297086
    Abstract: An interconnection structure and a package structure are provided. The interconnection structure includes a substrate, a conductive layer, a bonding layer, and a moderating layer. The conductive layer is over the substrate and has a top surface. The bonding layer is over the top surface of the conductive layer. The moderating layer is between the conductive layer and the bonding layer and configured to mitigate an increase in a surface roughness of the top surface of the conductive layer during an electroless plating process for forming the bonding layer.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 5, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Wei CHIANG, Yun-Ching HUNG, Yung-Sheng LIN
  • Publication number: 20240266167
    Abstract: A semiconductor device includes a semiconductor substrate having a first lattice constant, a fin-shape base protruding from the semiconductor substrate and extending lengthwise in a first direction, nanostructures suspended above the fin-shape base, a metal gate structure wrapping around each of the nanostructures, an epitaxial feature abutting the nanostructures, and inner spacers interposing the epitaxial feature and the metal gate structure. In a cross section perpendicular to the first direction the fin-shape base includes a first layer and a second layer over the first layer. The first layer has a second lattice constant different from the first lattice constant, and the second layer has a third lattice constant different from the second lattice constant. A portion of the metal gate structure is sandwiched between the second layer and a bottommost one of the nanostructures.
    Type: Application
    Filed: March 4, 2024
    Publication date: August 8, 2024
    Inventors: Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang, Kuo-Hua Pan
  • Publication number: 20190362034
    Abstract: A design method for civil engineering of reality scenery includes: selecting at least a reference point at a construction site, having a coordinate of the construction site defined as an absolute coordinate, establishing a three-dimensional (3D) model of a real scene, having a coordinate of the 3D model defined as a relative coordinate relative to the absolute coordinate of the construction site, calibrating the relative coordinate corresponding to the absolute coordinate and converting the relative coordinate into the absolute coordinate, incorporating virtual 3D objects into the 3D model, synchronously displaying the projected view of the 3D model as observed through a specific viewing angle, on a display device, and setting up a statistic database for synchronously recording the virtual 3D object as input into the 3D model or objects as removed from the 3D model, and outputting the statistic data from the statistic database through an output device.
    Type: Application
    Filed: April 2, 2019
    Publication date: November 28, 2019
    Inventor: Chun-Sheng Chiang
  • Publication number: 20180204153
    Abstract: An architectural planning method comprises: A. Receiving an authorization instruction as sent from a client's end to a main controller (or architect); B. Obtaining a real image composed of a master or main image of the designated main area of the architectural planning, and a peripheral image of a surrounding area around the main area, and transmitting the real image to a rear-end processing unit; C. Producing a three-dimensional or 3D image model as originated from the real image; D. Further implementing a 3D virtual architectural construction image into a designated coordinate area in the 3D image model; and E. Compiling the 3D image model and 3D virtual construction image to be a 3D architectural planning image.
    Type: Application
    Filed: November 27, 2017
    Publication date: July 19, 2018
    Inventor: Chun-Sheng Chiang
  • Publication number: 20130291851
    Abstract: A cutting method for crackly plate-shaped work piece and a cutting device thereof. The cutting method includes steps of: using a holding mold set to hold two faces of the crackly plate-shaped work piece along a predetermined cutting line and hold a product section of the crackly plate-shaped work piece that is to remain; and making a cutting mold move toward the crackly plate-shaped work piece by a stroke or up and down bite and cut the crackly plate-shaped work piece so as to cut off the crackly plate-shaped work piece along an edge of the holding mold set in alignment with the predetermined cutting line.
    Type: Application
    Filed: March 28, 2013
    Publication date: November 7, 2013
    Inventor: CHUN-SHENG CHIANG
  • Publication number: 20050028479
    Abstract: A method for forming caves on a construction, including steps of: preparing an envelope corresponding to the cave to be formed on the construction. Filling a fluid such as a gas or a liquid into the envelope to form a solid envelope; embedding the envelope in the construction to be grouted to define a grouting mold cavity. Deflating or draining the envelope of the fluid after a filling filled in the grouting mold cavity is hardened to achieve a construction with the caves.
    Type: Application
    Filed: August 8, 2003
    Publication date: February 10, 2005
    Inventor: Chun-Sheng Chiang