Abstract: An image processing method is provided. Firstly, input data including a number of original data are received. Next, the original data are converted into a number of converted emulation voltage signals. Then, at least a simulation circuit model including at least a spatial data node, at least a diffusion node and at least a connection device is established, wherein, the at least a connection device is coupled to a part or all of the at least a spatial data node and the at least a diffusion node. Afterwards, a part or all of the converted emulation voltage signals are supplied to the diffusion node to achieve voltage diffusion among the spatial data nodes and the diffusion nodes via the connection device, so that at least a diffused emulation voltage signal is obtained on the diffusion nodes. After that, processed image data are generated according to the diffused emulation voltage signals.

Abstract: The present invention discloses a temperature-sensing uninterruptible power supply system and a method for controlling the same. The temperature-sensing uninterruptible power supply system comprises a data processing device, an uninterruptible power supply device, a human temperature sensing module, and a monitoring software; the control method comprises the steps of: the human temperature sensing module detecting a human temperature in a specific distance range; the monitoring software determining whether a user leave from the specific distance range; the uninterruptible power supply device switching to a power-saving mode and commanding the data processing device to shot down; the human temperature sensing module detecting that the user is back to the specific distance range; and restarting the uninterruptible power supply device and commanding the data processing device to reboot.

Abstract: A reset signal generating circuit for a processor includes a charging circuit, a discharging circuit, and a triggering circuit. The charging circuit receives timing pulse signals from the processor to supply charging current according to the timing pulse signals when the processor operates normally, and stops supplying the charging current when the processor is at fault. The discharging circuit buffers the charging current supplied by the charging circuit when the processor operates normally, and discharges a low voltage to the triggering circuit when the processor is at fault. The triggering circuit outputs a trigger signal to the processor when the triggering circuit detects the low voltage to reset the processor.

Abstract: An exemplary control system for multiple light sources includes a clock circuit, a frequency dividing circuit, a recombining circuit, a power control circuit, and a triggering circuit. The clock circuit is configured to output a plurality of clock signals. The frequency dividing circuit is configured to divide the frequency of the clock signals to get a number of reference clock signals. The recombining circuit is configured to recombine the reference clock signals to get a plurality of timing signals. The power control circuit is configured to output electrical power to the multiple light sources according to the timing signals. The triggering circuit is configured to power on the light sources according to a received command.

Abstract: An audio data processing device and method includes selecting one multiple-S-curves, and running an interpolation arithmetic upon original points according to the selected multiple-S-curve. Selecting one multiple-S-curve includes selecting one of a plurality of S-curves corresponding to a current utilization ratio of a processor, obtaining audio data having a fixed length including sampling frequencies and the original points of the obtained audio data, and selecting the one multiple-S-curves corresponding to the selected S-curve and the obtained sampling frequencies.

Abstract: A method for generating image depth of a stereo image is provided. The method includes the following steps. Firstly, a stereo image is received. Next, a number of paths with greater gradient are searched in the stereo image. Then, the image depths of a number of first pixels in the paths are generated. After that, the image depths of a number of second pixels not in the paths are generated according to the image depths of the first pixels.

Abstract: An exemplary audio processing system includes a gain control unit, a sampling unit, and a triggering unit. The gain control unit is configured for amplifying an audio signal. The sampling unit is configured for sampling the audio signal. The triggering unit is configured for generating a gain reduction unit if the amplitude exceeds a predetermined value over a predetermined time period. The first predetermined value is set so that if the amplitude of the audio signal exceeds the predetermined value and the gain of the gain control unit is not reduced, the amplitude of the amplified audio signal exceeds a predetermined acceptable range. The gain control unit is also configured for reducing the gain of the gain control unit responding to the gain reduction signal to limit the amplitude of the amplified audio signal within the predetermined acceptable range.

Abstract: A surge protection circuit acquires a surge signal of a left channel (LC) signal line and a right channel (RC) signal line. After the surge signal transmitting on the LC signal line and the RC signal line are removed, an audio signal outputted from a signal input device are transmitted to an audio output device via the LC signal line and the RC signal line.

Abstract: A holographic recoding medium is provided, having holographic pages. Each page has reference mark (RM) placement areas at fixed locations for placing RM patterns. The reference marks are used to calibrate data images of data areas each of which is enclosed by at least three RM regions. Hidden information of the medium is stored by an specific encoded pattern based on existence, types and arrangements of the RM marks.

Abstract: A low-pass filter includes a first curved microstrip, a second curved microstrip, a first flat microstrip, a second flat microstrip, and a third flat microstrip. The first curved microstrip is in an n-shape and defines a first receiving space therein. The second curved microstrip is in an n-shape and defines a second receiving space therein. The first flat microstrip is received in the first receiving space and connected to a topside of the n shape of the first curved microstrip. The second flat microstrip is received in the first receiving space along with the first flat microstrip and connected to one end of the first curved microstrip. The third flat microstrip is received in the second receiving space and connected to one end of the second curved microstrip.

Abstract: An electronic device stores audio data and digital right information, determines zero crossing rate of the audio data store in the memory module. The zero crossing rate is embedded in the audio data and indicates a rate at which the voltage of the audio data changes from positive to negative or back during a time period, the electronic device then reads the audio data, and searches special audio data in the audio data. The audio data with the zero crossing rate more than a constant is defined as the special audio data. The electronic device reads the digital copyright information, and writes the digital copyright information into the special audio data.

Abstract: A power-on reset circuit, connected to an external direct current (DC) power source, to receive DC power signals and generate a reset signal, includes a delay circuit, a combination circuit and a shaping circuit. The delay circuit comprises a plurality of delay units, to delay the received DC power signals and output a plurality of delayed DC power signals. The combination circuit is connected to the delay circuit, to combine the delayed DC power signals into a combination signal, and output the combination signal. The shaping circuit is connected to and turns the combination circuit on and off according to the combination signal and outputs the reset signal.

Abstract: An inrush limiting circuit is connected between an external power source and a plurality of capacitors, and includes a delay trigger signal generator, a plurality of reversing circuits and a plurality of transmission gates. The delay trigger signal generator is connected to the external power source, to receive external power signals and generate a plurality of delay trigger signals. The reversing circuits are connected to the delay trigger signal generator, to reverse the delay trigger signals and output a plurality of the reversed delay trigger signals. The transmission gates are correspondingly connected to the delay trigger signal generator, the reversing circuits and the capacitors, to turn on respectively at different times based on the delay trigger signals and the reversed delay trigger signals, to cause the external power source to charge the capacitors at the different times so as to avoid an inrush current.

Abstract: A video processing device includes a processor, a voltage conversion circuit, and a Syndicat des Constructeurs d'Appareils Radiorécepteurs et Téléviseurs (SCART) chip. The processor is operable to process video signals, and control a GPIO (general purpose input output) pin to output different mode controlling signals according to different video signal formats. The voltage conversion circuit connected to the GPIO pin is operable to receive the mode controlling signals, and output different voltage signals according to the different format controlling signals. The SCART chip connected to the voltage conversion circuit is operable to receive the video signals and the voltage signals, and process the video signals according to the corresponding voltage signals.

Abstract: An electronic device generates universal asynchronous receiver/transmitter (UART) signals suitable to be transmitted via an audio port of the electronic device. The electronic device comprises a storing module, a reading module, an audio register, a controller and a processor. The store module stores debug or repair data comprising a plurality of bytes. The read module reads the plurality of bytes of the data one by one. The audio register generates a first audio signal and a second audio signal via the audio port. The controller controls the audio register to output the first or second audio signal according to binary numbers of a start bit, eight data bits, a parity bit and a stop bit of the UART signals. The processor executes operations of the storing module, the reading module, the audio register and the controller.

Abstract: An inrush limiting circuit is connected between an external power source and a plurality of capacitors, and includes a delay trigger signal generator, a plurality of reversing circuits and a plurality of transmission gates. The delay trigger signal generator is connected to the external power source, to receive external power signals and generate a plurality of delay trigger signals. The reversing circuits are connected to the delay trigger signal generator, to reverse the delay trigger signals and output a plurality of the reversed delay trigger signals. The transmission gates are correspondingly connected to the delay trigger signal generator, the reversing circuits and the capacitors, to turn on respectively at different times based on the delay trigger signals and the reversed delay trigger signals, to cause the external power source to charge the capacitors at the different times so as to avoid an inrush current.

Abstract: A reset signal generating circuit for a processor includes a charging circuit, a discharging circuit, and a triggering circuit. The charging circuit receives timing pulse signals from the processor to supply charging current according to the timing pulse signals when the processor operates normally, and stops supplying the charging current when the processor is at fault. The discharging circuit buffers the charging current supplied by the charging circuit when the processor operates normally, and discharges a low voltage to the triggering circuit when the processor is at fault. The triggering circuit outputs a trigger signal to the processor when the triggering circuit detects the low voltage to reset the processor.

Abstract: A power-on reset circuit connected to an external DC power source includes a delay circuit, a rectifying circuit, and a logic operation circuit. The delay circuit includes a first delay unit used for outputting a first delaying reference signal and a second delay unit used for outputting a second delaying reference signal. The rectifying circuit connected to the delay circuit includes a first rectifying unit and a second rectifying unit. The first rectifying unit is connected to the first delay circuit used for rectifying the first delaying reference signal to output a first rectified signal. The second rectifying unit is connected to the second delay circuit used for rectifying the second delaying reference signal to output a second rectified signal. The logic operation circuit is connected to the rectifying circuit used for outputting a reset signal according to the first rectified signal and the second rectified signal.

Abstract: A computer-implemented packet detection method includes a source at a first address transmitting packets to a terminal at a second address without transmitting the packets to any intermediate address during the transmission, the terminal receiving the packets, the terminal reassembling the received packets; the terminal performing a process referring to the reassembled packets, and the terminal transmitting packets to a destination at a third address which is different from the first address without transmitting the adjusted packets to any intermediate address during the transmission. Without extra operations and packet traffic, the computer-implemented packet detection method can be applied to virus detection, malicious content detection, or some statistics.

Abstract: A low-pass filter includes a first curved microstrip, a second curved microstrip, a first flat microstrip, a second flat microstrip, and a third flat microstrip. The first curved microstrip is in an n-shape and defines a first receiving space therein. The second curved microstrip is in an n-shape and defines a second receiving space therein. The first flat microstrip is received in the first receiving space and connected to a topside of the n shape of the first curved microstrip. The second flat microstrip is received in the first receiving space along with the first flat microstrip and connected to one end of the first curved microstrip. The third flat microstrip is received in the second receiving space and connected to one end of the second curved microstrip.