Abstract: The present invention provides a method for manufacturing bipolar transistors having reduced parasitic resistance and therefore improved performance compared to conventionally made bipolar transistors. Dry etching of a compound semiconductor in the transistor allows a perimeter of the compound semiconductor layer to be substantially coextensive with a perimeter of an overlying metal layer. This, in turn, reduces the gap between the compound semiconductor and subsequently deposited metal layer to be minimized, thereby reducing the parasitic resistance of the bipolar transistor.

Abstract: An integrated circuit includes a semiconductor substrate with semiconductor devices formed therein and thereon, a first wiring layer located over the substrate, a second wiring layer located on the first wiring layer, and a capacitor. The capacitor has metal-based charge-storage electrodes that extend through the second wiring layer and at least part of the first wiring layer. The wiring layers have interconnect wire embedded therein.

Abstract: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.

Abstract: A method for making an ICD or MEOD structure includes dry etching a structure to produce one or more via holes in an upper layer of the structure. The dry etching step stops on a metal layer that underlies the upper layer in the structure. The method also includes cleaning the dry etched structure with an aqueous solution that includes hydrogen peroxide and either an ammonium salt or an amine salt.

Abstract: An integrated circuit includes a semiconductor substrate with semiconductor devices formed therein and thereon, a first wiring layer located over the substrate, a second wiring layer located on the first wiring layer, and a capacitor. The capacitor has metal-based charge-storage electrodes that extend through the second wiring layer and at least part of the first wiring layer. The wiring layers have interconnect wire embedded therein.

Abstract: A process for fabricating a silicon-on-insulator integrated circuit in conjunction with a process for shallow trench isolation is disclosed. The shallow trench isolation is performed to define active regions in the silicon substrate. The active regions are electrically isolated from each other by regions of silicon dioxide formed in the substrate by the shallow trench isolation process. The height of the silicon dioxide regions above the substrate surface defines the combined thickness of the islands of silicon dioxide and the silicon formed over the islands of silicon dioxide. A mask is then formed on the silicon substrate with the regions of silicon dioxide formed therein. The mask defines the regions on the silicon substrate surface on which the islands of silicon dioxide are to be formed. The silicon dioxide islands are formed with the mask in place, and the mask is subsequently removed. Single crystal silicon is formed epitaxially on the structure.

Abstract: The invention is directed to a process for forming p+ and n+ gates on a single substrate. A polycrystalline silicon or amorphous silicon layer is formed on a substrate with n-type and p-type regions formed therein and with a layer of silicon dioxide formed thereover and the structure is subjected hobo a low temperature anneal. A layer of metal silicide is then formed over the structure and n-type and p-type dopants are implanted into the resulting structure. A nitrogen implant is selectively performed in the portion of the metal silicide layer overlying a field oxide region that separates the n-type region from the p-type region in the substrate surface. The nitrogen implant reduces the amount to which the p-type dopant diffuses through the silicide layer and into the n+ gates. A dielectric material is then formed over the structure and patterned, after which the structure is subjected to additional processing steps to form gate stacks over the n-regions and the p-regions of the substrate.

Abstract: An integrated circuit device in which the gate oxide of the devices in the integrated circuit device is selected to control plasma damage during device processing is disclosed. The integrated circuit device has at least two transistors, each transistor having a source, drain, gate and channel. At least one device has a channel length that is greater than 0.5 .mu.m and at least one device has a channel length that is less than 0.5 .mu.m. The device having a channel length that is greater than 0.5 .mu.m has a gate oxide thickness that is less than the gate oxide thickness of the device having a channel length that is less than 0.5 .mu.m. The relative thickness of the gate oxide for the shorter channel devices and the longer channel devices is selected so that the tunneling leakage current that passes through the gate oxide for the longer channel devices is at least two orders of magnitude greater than the tunneling current through the gate oxide of the shorter channel devices.

Abstract: A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

Abstract: A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.

Abstract: A method of preventing diffusion penetration of the dopant used to dope polysilicon gate material in a MOSFET is disclosed. Atomic nitrogen is introduced into the substrate prior to gate oxide growth. The nitrogen later diffuses upward into the gate oxide and blocks subsequent ion implanted gate dopants from penetrating to the substrate. Low dosages of atomic nitrogen implantation, while not significantly affecting gate oxide growth rate, produce significant improvements in the damage immunity of thin gate oxides.

Abstract: A method of integrated circuit fabrication is disclosed. Layers of silicon nitride and silicide dioxide are formed upon a silicon substrate. These layers are etched to create a channel having the width of the intended gate. The silicon dioxide is then wet etched. Next, polysilicon is deposited within the channel. The silicon dioxide and the silicon nitride layers are then removed. A T-shaped polysilicon gate facilitates the formation of rectangular-shaped silicon nitride spacers. Subsequent salicidation is performed.

Abstract: The longitudinal edges of the overlying channel layer of a thin-film transistor are substantially aligned with the longitudinal edges of the underlying polysilicon gate layer. As a result of this line-on-line arrangement of the channel and gate layers, integration area is minimized so that optimum integration density is achieved. Source-to-drain on current is increased as the result of the increased channel width gained from the sidewall section of the polysilicon gate, which may occur as a result of the permissible lateral extension of the body (channel) layer over one longitudinal edge of the channel gate layer due to a misalignment in lithography or processing delta.

Abstract: A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

Abstract: A six-transistor SRAM of a high-density memory comprises two thin-film n-channel pull-down transistors and four conventional p-channel load and access transistors. As embodied in a semiconductor chip, the cell is simpler than priorly known six-transistor cells and is relatively immune from the deleterious effects of sodium ions and hot-carrier aging.

Abstract: An integrated circuit device having reduced-height gate stack is fabricated by using a patterned oxide hard mask to pattern the underlying metal layer. The oxide mask is removed and the patterned metal is subsequently used as a mask to etch the polysilicon layer.

Abstract: A field effect transistor is fabricated with an ion implanted silicide layer and a conducting diffusion barrier pad layer that acts as a diffusion mask. The dopants from the silicide layer are diffused into the substrate to form shallow source/drain regions.

Abstract: A field effect transistor is fabricated with a window pad layer that is patterned using a patterned dielectric with sublithographic spacing as an etch mask. Desirable attributes of the transistor include small junction capacitance.

Abstract: Shallow junctions n- and p-channel field effect transistors are formed with a single ion implant into a conformal tungsten silicide layer. Although phosphorous and boron are implanted into the same silicide regions, the phosphorous prevents the boron from outdiffusing.

Abstract: Disclosed are novel fast semiconductor photodetector means that comprise a good asymmetric superlattice structure. Associated with the material of the structure is a relatively short minority carrier effective lifetime .tau..sub.e, typically .tau..sub.e <10.sup.-9 sec. In response to a constant photon flux of appropriate wavelength the photodetector can have a substantially constant voltage output that is proportional to the photon flux for small values of flux, and that saturates at a value that is substantially proportional to .tau..sub.e.sup.-1 for relatively large values of flux. The novel photodetector means can be advantageously combined with a FET or bipolar transistor, and the combination can be part of an integrated circuit.