Patents by Inventor Chun-Tsung Kuo

Chun-Tsung Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948969
    Abstract: A semiconductor structure includes a substrate, at least one dielectric layer and a capacitor structure. The at least one dielectric layer is disposed over the substrate, and the at least one dielectric layer includes a step edge profile. The capacitor structure is disposed over the substrate. The capacitor structure includes a bottom electrode, a capacitor dielectric layer and a top electrode. The bottom electrode covers the step edge profile of the at least one dielectric layer and has a first step profile substantially conformal to the step edge profile of the at least one dielectric layer. The capacitor dielectric layer covers the bottom electrode and has a second step profile substantially conformal to the first step profile. The top electrode covers the capacitor dielectric layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming Chyi Liu, Chun-Tsung Kuo
  • Publication number: 20240047510
    Abstract: A fabrication method includes: forming, over a first dielectric layer between a first metal portion and a second metal portion, a thin film resistor (TFR); forming openings in the first dielectric layer over the first metal portion and the second metal portion; and forming a first bond pad in an opening over the first metal portion and a second bond pad in an opening over the second metal portion; wherein the first dielectric layer is disposed between the first bond pad and the second bond pad, the TFR is formed over the first dielectric layer between the first bond pad and the second bond pad, the TFR has an electrical connection at a first end to the first bond pad and an electrical connection at a second end to the second bond pad, and the TFR provides a resistive path between the first bond pad and the second bond path.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Tsung Kuo, Ming Chyi Liu
  • Patent number: 11869761
    Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Chun-Tsung Kuo, Jiech-Fun Lu, Min-Ying Tsai, Chiao-Chun Hsu, Ching I Li
  • Publication number: 20230378230
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a plurality of photodetectors disposed within a substrate, and the plurality of photodetectors includes a first active photodetector and a black level correction (BLC) photodetector. A metal grid structure surrounds the first active photodetector along a periphery of the first active photodetector on a first side of the substrate. A recessed blocking structure covers the BLC photodetector on the first side of the substrate. The recessed blocking structure includes both a first blocking layer inset into the first side of the substrate and a second blocking layer directly over the first blocking layer.
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Inventors: Chun-Tsung Kuo, Jiech-Fun Lu
  • Publication number: 20230361204
    Abstract: A BJT and methods of forming the same are described. The BJT includes a collector region disposed in a substrate, a lower base structure disposed on the collector region, a first dielectric layer surrounding a bottom portion of the lower base structure, and a second dielectric layer surrounding a top portion of the lower base structure. The first dielectric layer includes a first oxide, the second dielectric layer includes a second oxide, and the first and second oxides have different densities. The BJT further includes an upper base structure disposed on the second dielectric layer and the lower base structure, an emitter region disposed on the lower base structure, a sidewall spacer structure disposed between the emitter region and the upper base structure, and the sidewall spacer structure includes a material different from materials of the first and second dielectric layers.
    Type: Application
    Filed: May 4, 2022
    Publication date: November 9, 2023
    Inventors: Chun-Tsung KUO, Chuan-Feng CHEN
  • Patent number: 11710783
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a bipolar junction transistor (BJT). A dielectric film is deposited over a substrate and comprises a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer between the lower and upper dielectric layers. A first semiconductor layer is deposited over the dielectric film and is subsequently patterned to form an opening exposing the dielectric film. A first etch is performed into the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer. Further, the first etch stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer. Additional etches are performed to extend the opening to the substrate. A lower base structure and an emitter are formed stacked in and filling the opening, and the first semiconductor layer is patterned to form an upper base structure.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: July 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Tsung Kuo, Jiech-Fun Lu
  • Publication number: 20230067299
    Abstract: A semiconductor structure includes a substrate, at least one dielectric layer and a capacitor structure. The at least one dielectric layer is disposed over the substrate, and the at least one dielectric layer includes a step edge profile. The capacitor structure is disposed over the substrate. The capacitor structure includes a bottom electrode, a capacitor dielectric layer and a top electrode. The bottom electrode covers the step edge profile of the at least one dielectric layer and has a first step profile substantially conformal to the step edge profile of the at least one dielectric layer. The capacitor dielectric layer covers the bottom electrode and has a second step profile substantially conformal to the first step profile. The top electrode covers the capacitor dielectric layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: MING CHYI LIU, CHUN-TSUNG KUO
  • Publication number: 20220384496
    Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Yu-Hung Cheng, Chun-Tsung Kuo, Jiech-Fun Lu, Min-Ying Tsai, Chiao-Chun Hsu, Ching I Li
  • Publication number: 20220262845
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an image sensor, the method includes forming a photodetector within a substrate. The substrate is etched to define a plurality of first protrusions over the photodetector. A first dielectric layer is deposited on the substrate. A second dielectric layer is deposited on the first dielectric layer. An etching process is performed on the first and second dielectric layers such that the first dielectric layer comprises a plurality of second protrusions different from the plurality of first protrusions. The first dielectric layer is etched more quickly than the second dielectric layer during the etching process.
    Type: Application
    Filed: May 3, 2022
    Publication date: August 18, 2022
    Inventors: Jiech-Fun Lu, Chun-Tsung Kuo
  • Patent number: 11335726
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a substrate including a plurality of sidewalls that define a plurality of protrusions along a first side of the substrate. The substrate has a first index of refraction. A photodetector is disposed within the substrate and underlying the plurality of protrusions. A plurality of micro-lenses overlying the first side of the substrate. The micro-lenses have a second index of refraction that is less than the first index of refraction. The micro-lenses are respectively disposed laterally between and directly contact an adjacent pair of protrusions in the plurality of protrusions. Further, the micro-lenses respectively comprise a convex upper surface.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiech-Fun Lu, Chun-Tsung Kuo
  • Publication number: 20220149147
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes depositing a resistive layer over a substrate. A conductive structure is formed over the resistive layer. A first etch process is performed on the resistive layer to define a resistor segment of the resistive layer and a peripheral region of the resistive layer. The resistor segment is laterally separated from the peripheral region of the resistive layer. The peripheral region continuously laterally wraps around an outer perimeter of the resistor segment.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 12, 2022
    Inventors: Chun-Tsung Kuo, Jiech-Fun Lu
  • Publication number: 20220077305
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a bipolar junction transistor (BJT). A dielectric film is deposited over a substrate and comprises a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer between the lower and upper dielectric layers. A first semiconductor layer is deposited over the dielectric film and is subsequently patterned to form an opening exposing the dielectric film. A first etch is performed into the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer. Further, the first etch stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer. Additional etches are performed to extend the opening to the substrate. A lower base structure and an emitter are formed stacked in and filling the opening, and the first semiconductor layer is patterned to form an upper base structure.
    Type: Application
    Filed: November 17, 2021
    Publication date: March 10, 2022
    Inventors: Chun-Tsung Kuo, Jiech-Fun Lu
  • Patent number: 11233117
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a resistor structure. A resistive layer overlies a substrate. The resistor structure overlies the substrate. The resistor structure includes a resistor segment of the resistive layer and conductive via structures overlying the resistor segment. A ring structure encloses the resistor structure. The ring structure extends continuously from a first point above the conductive structures to a second point below a bottom surface of the resistive layer.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Tsung Kuo, Jiech-Fun Lu
  • Patent number: 11183587
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a bipolar junction transistor (BJT). A dielectric film is deposited over a substrate and comprises a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer between the lower and upper dielectric layers. A first semiconductor layer is deposited over the dielectric film and is subsequently patterned to form an opening exposing the dielectric film. A first etch is performed into the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer. Further, the first etch stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer. Additional etches are performed to extend the opening to the substrate. A lower base structure and an emitter are formed stacked in and filling the opening, and the first semiconductor layer is patterned to form an upper base structure.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Tsung Kuo, Jiech-Fun Lu
  • Publication number: 20210335861
    Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.
    Type: Application
    Filed: September 11, 2020
    Publication date: October 28, 2021
    Inventors: Yu-Hung Cheng, Chun-Tsung Kuo, Jiech-Fun Lu, Min-Ying Tsai, Chiao-Chun Hsu, Ching I Li
  • Patent number: 11133374
    Abstract: A method includes depositing a magnetic layer over a dielectric layer, and etching a first portion of the magnetic layer, in which a second portion of the magnetic layer that is directly under the first portion of the magnetic layer remains over the dielectric layer after etching the first portion of the magnetic layer. The second portion of the magnetic layer is etched.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Shuo Su, Chun-Tsung Kuo, Jiech-Fun Lu
  • Publication number: 20210134940
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a resistor structure. A resistive layer overlies a substrate. The resistor structure overlies the substrate. The resistor structure includes a resistor segment of the resistive layer and conductive via structures overlying the resistor segment. A ring structure encloses the resistor structure. The ring structure extends continuously from a first point above the conductive structures to a second point below a bottom surface of the resistive layer.
    Type: Application
    Filed: February 13, 2020
    Publication date: May 6, 2021
    Inventors: Chun-Tsung Kuo, Jiech-Fun Lu
  • Publication number: 20210134988
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a bipolar junction transistor (BJT). A dielectric film is deposited over a substrate and comprises a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer between the lower and upper dielectric layers. A first semiconductor layer is deposited over the dielectric film and is subsequently patterned to form an opening exposing the dielectric film. A first etch is performed into the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer. Further, the first etch stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer. Additional etches are performed to extend the opening to the substrate. A lower base structure and an emitter are formed stacked in and filling the opening, and the first semiconductor layer is patterned to form an upper base structure.
    Type: Application
    Filed: July 9, 2020
    Publication date: May 6, 2021
    Inventors: Chun-Tsung Kuo, Jiech-Fun Lu
  • Publication number: 20210134875
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a substrate including a plurality of sidewalls that define a plurality of protrusions along a first side of the substrate. The substrate has a first index of refraction. A photodetector is disposed within the substrate and underlying the plurality of protrusions. A plurality of micro-lenses overlying the first side of the substrate. The micro-lenses have a second index of refraction that is less than the first index of refraction. The micro-lenses are respectively disposed laterally between and directly contact an adjacent pair of protrusions in the plurality of protrusions. Further, the micro-lenses respectively comprise a convex upper surface.
    Type: Application
    Filed: February 28, 2020
    Publication date: May 6, 2021
    Inventors: Jiech-Fun Lu, Chun-Tsung Kuo
  • Publication number: 20200066832
    Abstract: A method includes depositing a magnetic layer over a dielectric layer, and etching a first portion of the magnetic layer, in which a second portion of the magnetic layer that is directly under the first portion of the magnetic layer remains over the dielectric layer after etching the first portion of the magnetic layer. The second portion of the magnetic layer is etched.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 27, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Shuo SU, Chun-Tsung KUO, Jiech-Fun LU