Patents by Inventor Chun-Tsung Kuo
Chun-Tsung Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10461145Abstract: A method for fabricating a magnetic core includes depositing a magnetic layer on a dielectric layer, forming a first photoresist layer on the magnetic layer and patterning the first photoresist layer, etching the magnetic layer through the patterned first photoresist layer, in which a first section of the magnetic layer exposed by the first photoresist layer remains on the dielectric layer after the magnetic layer is etched, removing the patterned first photoresist layer, forming a second photoresist layer on the magnetic layer and patterning the second photoresist layer, etching the magnetic layer through the patterned second photoresist layer, and removing the second photoresist layer.Type: GrantFiled: January 25, 2018Date of Patent: October 29, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Shuo Su, Chun-Tsung Kuo, Jiech-Fun Lu
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Patent number: 10170601Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a collector element formed in or over a semiconductor substrate. The semiconductor device structure also includes a semiconductor element over the collector element, and the semiconductor element has a top surface, a bottom surface, and a side surface. The semiconductor device structure further includes an emitter element over the top surface of the semiconductor element. In addition, the semiconductor device structure includes a base element over the collector element and in direct contact with the side surface of the semiconductor element.Type: GrantFiled: September 6, 2017Date of Patent: January 1, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Tsung Kuo, Chuan-Feng Chen
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Patent number: 10103287Abstract: A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes an active area on a substrate, where the active area is at least one of a p-type region or an n-type region. The substrate includes a well, where the well is a p-well when the active area is a p-type region, and the well is an n-well when the active area is an n-type region. The well includes a photodiode. The active area is connected to a voltage supply having a voltage level, such as ground. The active area on the substrate increases a distance between the photodiode and the active area, which reduces junction leakage as compared to a semiconductor arrangement where the active area is formed at least partially within the substrate.Type: GrantFiled: January 7, 2014Date of Patent: October 16, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kai-Chun Hsu, Shyh-Fann Ting, Jhy-Jyi Sze, Chun-Tsung Kuo, Ching-Chun Wang, Dun-Nian Yaung
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Publication number: 20180166564Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a collector element formed in or over a semiconductor substrate. The semiconductor device structure also includes a semiconductor element over the collector element, and the semiconductor element has a top surface, a bottom surface, and a side surface. The semiconductor device structure further includes an emitter element over the top surface of the semiconductor element. In addition, the semiconductor device structure includes a base element over the collector element and in direct contact with the side surface of the semiconductor element.Type: ApplicationFiled: September 6, 2017Publication date: June 14, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Tsung KUO, Chuan-Feng CHEN
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Publication number: 20180166527Abstract: A method for fabricating a magnetic core includes depositing a magnetic layer on a dielectric layer, forming a first photoresist layer on the magnetic layer and patterning the first photoresist layer, etching the magnetic layer through the patterned first photoresist layer, in which a first section of the magnetic layer exposed by the first photoresist layer remains on the dielectric layer after the magnetic layer is etched, removing the patterned first photoresist layer, forming a second photoresist layer on the magnetic layer and patterning the second photoresist layer, etching the magnetic layer through the patterned second photoresist layer, and removing the second photoresist layer.Type: ApplicationFiled: January 25, 2018Publication date: June 14, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Shuo SU, Chun-Tsung KUO, Jiech-Fun LU
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Patent number: 9893141Abstract: A magnetic core includes a center section having a substantially uniform thickness, and an edge section connected to and surrounding the center section. The edge section includes a bottom portion and a top portion disposed on the bottom portion, in which the bottom portion has a gradual side surface since the top portion has a steep side surface. The profile of the magnetic core can be more rectangular thereby providing better inductor performance.Type: GrantFiled: February 26, 2015Date of Patent: February 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Shuo Su, Chun-Tsung Kuo, Jiech-Fun Lu
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Patent number: 9799721Abstract: A method of forming a semiconductor device includes forming a lower coil segment in a first dielectric layer over a substrate, forming a second dielectric layer over the lower coil segment and the first dielectric layer, anisotropically etching a top portion of the second dielectric layer to form an opening over the lower coil segment, depositing magnetic material in the opening to form a magnetic core, forming a third dielectric layer over the magnetic core and the second dielectric layer, forming vias extending through the second dielectric layer and the third dielectric layer, and after forming the vias, forming an upper coil segment over the third dielectric layer and the magnetic core, wherein the vias connect the upper coil segment with the lower coil segment.Type: GrantFiled: April 17, 2015Date of Patent: October 24, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Tsung Kuo, Jiech-Fun Lu, Yen-Shuo Su
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Publication number: 20160307991Abstract: A method of forming a semiconductor device includes forming a lower coil segment in a first dielectric layer over a substrate, forming a second dielectric layer over the lower coil segment and the first dielectric layer, anisotropically etching a top portion of the second dielectric layer to form an opening over the lower coil segment, depositing magnetic material in the opening to form a magnetic core, forming a third dielectric layer over the magnetic core and the second dielectric layer, forming vias extending through the second dielectric layer and the third dielectric layer, and after forming the vias, forming an upper coil segment over the third dielectric layer and the magnetic core, wherein the vias connect the upper coil segment with the lower coil segment.Type: ApplicationFiled: April 17, 2015Publication date: October 20, 2016Inventors: Chun-Tsung Kuo, Jiech-Fun Lu, Yen-Shuo Su
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Publication number: 20160254342Abstract: A magnetic core includes a center section having a substantially uniform thickness, and an edge section connected to and surrounding the center section. The edge section includes a bottom portion and a top portion disposed on the bottom portion, in which the bottom portion has a gradual side surface since the top portion has a steep side surface. The profile of the magnetic core can be more rectangular thereby providing better inductor performance.Type: ApplicationFiled: February 26, 2015Publication date: September 1, 2016Inventors: Yen-Shuo SU, Chun-Tsung KUO, Jiech-Fun LU
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Publication number: 20150155326Abstract: A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes an active area on a substrate, where the active area is at least one of a p-type region or an n-type region. The substrate includes a well, where the well is a p-well when the active area is a p-type region, and the well is an n-well when the active area is an n-type region. The well includes a photodiode. The active area is connected to a voltage supply having a voltage level, such as ground. The active area on the substrate increases a distance between the photodiode and the active area, which reduces junction leakage as compared to a semiconductor arrangement where the active area is formed at least partially within the substrate.Type: ApplicationFiled: January 7, 2014Publication date: June 4, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kai-Chun Hsu, Shyh-Fann Ting, Jhy-Jyi Sze, Chun-Tsung Kuo, Ching-Chun Wang, Dun-Nian Yaung
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Patent number: 8987033Abstract: A method includes forming a blocking layer over a substrate, and etching the blocking layer to form a trench in the blocking layer. A dielectric layer is formed, wherein the dielectric layer comprises a first portion over the blocking layer, and a second portion in the trench. After the step of forming the dielectric layer, an implantation is performed to implant an impurity into the substrate to form a deep well region. After the implantation, the dielectric layer and the blocking layer are removed.Type: GrantFiled: August 2, 2011Date of Patent: March 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Chung Su, Shih-Chang Liu, Shih Pei Chou, Chia-Shiung Tsai, Chun-Tsung Kuo, Wen-I Hsu, Yi-Shin Chu
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Patent number: 8883524Abstract: Methods and apparatus for a sensor are disclosed. An oxide layer is formed on a substrate, followed by a spacer layer and a buffer layer. A photoresist layer is formed on the buffer layer over a pixel region, with an opening exposing a first part of the buffer layer. A first etching is performed to remove the first part of the buffer layer to expose a first part of the spacer layer. A second etching is performed to remove the first part of the spacer layer, the remaining buffer layer, and partially remove a second part of the spacer layer so that the result spacer layer will have an end with a shape substantially similar to a triangle, a height of the end is in a substantially same range as a length of the end.Type: GrantFiled: June 3, 2013Date of Patent: November 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Tsung Kuo, Jiech-Fun Lu, Yeur-Luen Tu, Chia-Shiung Tsai
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Publication number: 20140264506Abstract: Methods and apparatus for a sensor are disclosed. An oxide layer is formed on a substrate, followed by a spacer layer and a buffer layer. A photoresist layer is formed on the buffer layer over a pixel region, with an opening exposing a first part of the buffer layer. A first etching is performed to remove the first part of the buffer layer to expose a first part of the spacer layer. A second etching is performed to remove the first part of the spacer layer, the remaining buffer layer, and partially remove a second part of the spacer layer so that the result spacer layer will have an end with a shape substantially similar to a triangle, a height of the end is in a substantially same range as a length of the end.Type: ApplicationFiled: June 3, 2013Publication date: September 18, 2014Inventors: Chun-Tsung Kuo, Jiech-Fun Lu, Yeur-Luen Tu, Chia-Shiung Tsai
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Patent number: 8501572Abstract: The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.Type: GrantFiled: September 2, 2010Date of Patent: August 6, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Tsung Kuo, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20130034929Abstract: A method includes forming a blocking layer over a substrate, and etching the blocking layer to form a trench in the blocking layer. A dielectric layer is formed, wherein the dielectric layer comprises a first portion over the blocking layer, and a second portion in the trench. After the step of forming the dielectric layer, an implantation is performed to implant an impurity into the substrate to form a deep well region. After the implantation, the dielectric layer and the blocking layer are removed.Type: ApplicationFiled: August 2, 2011Publication date: February 7, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Chung Su, Shih-Chang Liu, Shih Pei Chou, Chia-Shiung Tsai, Chun-Tsung Kuo, Wen-I Hsu, Yi-Shin Chu
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Publication number: 20120235280Abstract: An integrated circuit includes a bipolar transistor disposed over a substrate. The bipolar transistor includes a base electrode disposed around at least one germanium-containing layer. An emitter electrode is disposed over the at least one germanium-containing layer. At least one isolation structure is disposed between the emitter electrode and the at least one germanium-containing layer. A top surface of the at least one isolation structure is disposed between and electrically isolating a top surface of the emitter electrode from a top surface of the at least one germanium-containing layer.Type: ApplicationFiled: March 14, 2011Publication date: September 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Tung HUANG, Chun-Tsung KUO, Shih-Chang LIU, Yeur-Luen TU
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Patent number: 8258545Abstract: An integrated circuit includes a bipolar transistor disposed over a substrate. The bipolar transistor includes a base electrode disposed around at least one germanium-containing layer. An emitter electrode is disposed over the at least one germanium-containing layer. At least one isolation structure is disposed between the emitter electrode and the at least one germanium-containing layer. A top surface of the at least one isolation structure is disposed between and electrically isolating a top surface of the emitter electrode from a top surface of the at least one germanium-containing layer.Type: GrantFiled: March 14, 2011Date of Patent: September 4, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Tung Huang, Chun-Tsung Kuo, Shih-Chang Liu, Yeur-Luen Tu
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Publication number: 20120056305Abstract: The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.Type: ApplicationFiled: September 2, 2010Publication date: March 8, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Tsung Kuo, Shih-Chang Liu, Chia-Shiung Tsai