Abstract: A graft polymer is provided, which includes a polymer backbone with a plurality of hydroxy groups, protection group modified histidine grafted onto the side of the polymer backbone, and hydrophilic polymer having terminal reactive group grafted onto the side of the polymer backbone. The graft polymer coating can be applied to metal material to form a composite material, which can be implanted into an organism to reduce adhesion problems.

Abstract: Methods, systems and apparatuses, including computer programs encoded on computer storage media, are provided for processing claims using both unstructured and structured policy documents and claim data. Policy rules, benefit calculation formulae, necessary data points, and benefit requirements are extracted from policy documents. Unstructured claim data is converted to a structured form using natural language processing, information extraction, and AI techniques to identify and extract relevant information, including values for the data points and benefit conditions, then the combined structured data and converted unstructured data is processed to get all values for the data points and applicable benefit conditions. The relevant claim information is then further processed according to the policy rules and benefit calculation formulae to generate a benefit payment amount and entitled additional benefits.

Abstract: A photoelectric detection circuit and a photoelectric detector are provided. The photoelectric detection circuit includes a first photoelectric sensing element and a second photoelectric sensing element, and an electrical characteristic of the first photoelectric sensing element is substantially identical to an electrical characteristic of the second photoelectric sensing element; the first photoelectric sensing element outputs a first sensed electrical signal, and the second photoelectric sensing element outputs a second sensed electrical signal; a polarity of the first sensed electrical signal is opposite to a polarity of the second sensed electrical signal, and an amplitude value of the first sensed electrical signal is substantially identical to an amplitude value of the second sensed electrical signal.

Abstract: A light source panel and a display device are disclosed. The display device includes: a display panel of reflection type and a light source panel disposed on a light emitting side of the display panel, the light source panel includes a parallax barrier structure and light emitting units, the parallax barrier structure includes light splitting components, the light splitting components include at least a non-transparent state, the light transmission areas are located in spaces between adjacent splitting light components, and the light emitting units at least partially overlap with the light splitting components in a direction perpendicular to the light source panel.

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Abstract: An optical lens assembly includes four lens elements which are, in order from an object side to an image side along an imaging optical path: a first lens element, a second lens element, a third lens element and a fourth lens element. The first lens element has positive refractive power. The second lens element has an image-side surface being concave in a paraxial region thereof. The third lens element has an object-side surface being concave in a paraxial region thereof. The fourth lens element with negative refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof, and at least one of the object-side surface and the image-side surface of the fourth lens element has at least one inflection point in an off-axis region thereof.

Abstract: In a method for manufacturing a semiconductor device, fin structures each having an upper portion and a lower portion, are formed. The lower portion is embedded in an isolation insulating layer disposed over a substrate and the upper portion protrudes the isolation insulating layer. A gate dielectric layer is formed over the upper portion of each of the fin structures. A conductive layer is formed over the gate dielectric layer. A cap layer is formed over the conductive layer. An ion implantation operation is performed on the fin structures with the cap layer. The ion implantation operation is performed multiple times using different implantation angles to introduce ions into one side surface of each of the fin structures.

Abstract: An image processing method includes the following steps: receiving a two-dimensional image and segmenting an object block in the two-dimensional image, masking the object block with a color block to generate a mask image; inputting the two-dimensional image and the mask image into a first image processing model, outputting a feature vector from the first image processing model; and inputting the two-dimensional image into a second image processing model to obtain a feature map. The feature map comprises a plurality of feature channel maps, and the feature vector contains a plurality of feature values. Each of the feature channel maps corresponds to one of the feature values in sequence. A weighted feature map is generated according to the feature channel maps and the feature values.

Abstract: A method for analyzing and evaluating facial muscle status includes following steps: capturing user's face image through an image capturing unit of a face image analyzing apparatus after it is activated; analyzing the face image through an analyzing algorithm for obtaining multiple ideal muscle identifying points corresponding to five sense features of a face in the face image; identifying the face image through a fuzzy comparison algorithm and a training model for obtaining multiple actual muscle identifying points corresponding to actual muscle status of the face in the face image; evaluating each of the actual muscle identifying points and generating evaluated results based on the multiple ideal muscle identifying points in company with a pre-stored evaluation rule; and, displaying the multiple ideal muscle identifying points, the multiple actual muscle identifying points and the evaluated results on a display of the face image analyzing apparatus.

Abstract: A method for automatically marking muscle feature points on face implemented by a face image analysis apparatus (1) includes following steps: obtaining a to-be-identified image (2) showing a face of a user; performing a face recognition procedure to the to-be-identified image (2) for obtaining multiple strong reference points on the face; performing a fuzzy comparison procedure on the face of the to-be-identified image (2) based on a pre-trained training model (153) for generating a comparison result; automatically marking multiple muscle feature points (3) on the face according to the comparison result, wherein the multiple muscle feature points (3) respectively locate at multiple weak reference points of the face; and, displaying the multiple muscle feature points (3) and the to-be-identified image (2) on a display unit (11).

Abstract: A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor over a substrate. The semiconductor device structure includes a dielectric structure over the substrate and covering the transistor. The semiconductor device structure includes a contact structure passing through the dielectric structure and electrically connected to the transistor. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer, the first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, a first lower portion of the first barrier layer is in direct contact with the dielectric structure, and a thickness of the first lower portion increases toward the substrate.

Abstract: A volume measuring apparatus having a first camera, a second camera, an emitting unit and a processing unit is disclosed. The processing unit controls the emitting unit to emit invisible structure light, and controls the first and second camera to capture a left and a right image both containing a target-box. The processing unit generates a depth graph according to the left and right image, and scans the depth graph through multiple scanning lines for determining a middle line, a bottom line, a left-sideline, and a right-sideline of the target-box in the depth graph. The processing unit performs scanning, within a range of the middle line, the bottom line, the left-sideline, and the right-sideline, for obtaining a plurality of width information, height information, and length information. The processing unit computes the volume related data of the target-box according to the plurality of width information, height information, and length information.

Abstract: In some embodiments, the present disclosure relates to a method of forming a multi-dimensional integrated chip. The method includes forming a first plurality of interconnect layers within a first dielectric structure on a front-side of a first substrate and forming a second plurality of interconnect layers within a second dielectric structure on a front-side of a second substrate. A first redistribution layer coupled to the first plurality of interconnect layers is bonded to a second redistribution layer coupled to the second plurality of interconnect layers along an interface. A recess is formed within a back-side of the second substrate and over the second plurality of interconnect layers. A bond pad is formed within the recess. The bond pad is laterally separated from the first redistribution layer by a non-zero distance.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure, disposed over the substrate; a gate structure, disposed over the substrate and covering a portion of the fin structure; a first sidewall, disposed over the substrate and surrounding a lower portion of the gate structure; and a second sidewall, disposed over the first sidewall and directly surrounding an upper portion of the gate structure, wherein the first sidewall is orthogonal to the second sidewall.

Abstract: The present disclosure provides a light-emitting layer, an organic light emitting diode (OLED) device, and a display apparatus. The light-emitting layer has a host material containing a first photocrosslinker group. A guest material containing a second photocrosslinker group is prepared. The host material and the guest material are mixed in a solvent to form a mixture. The mixture is coated, annealed, and LV-irradiated on a substrate to form the light-emitting layer. As such, the disclosed light-emitting layer is prepared by the polymerization after being on the substrate. The light-emitting layer has a mesh structure. The mesh structure improves energy transfer between the host material and guest material and increases the lifespan of the resultant OLED device and OLED display apparatus.

Abstract: A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.

Abstract: A method of very high throughput (VHT) operation information subfields design for IEEE 802.11 WLAN is proposed. The VHT operation information subfields comprise a channel width, a channel center frequency segment 0 (CCFS0), and a channel center frequency segment 1 (CCFS1). Multiple definitions of the VHT operation information subfields have been adopted by different access points (AP)s and wireless stations (STAs). In accordance with one novel aspect, upon receiving the VHT operation information element broadcasted by an AP, an STA will first check the channel width indicated by the AP. The STA then follows different definitions under different channel widths. Under such method, the STA can support up to 160 MHz operation mode with APs following different definitions and operating up to 160 MHz mode.

Abstract: A latent code defined in an input space is processed by the mapping neural network to produce an intermediate latent code defined in an intermediate latent space. The intermediate latent code may be used as appearance vector that is processed by the synthesis neural network to generate an image. The appearance vector is a compressed encoding of data, such as video frames including a person's face, audio, and other data. Captured images may be converted into appearance vectors at a local device and transmitted to a remote device using much less bandwidth compared with transmitting the captured images. A synthesis neural network at the remote device reconstructs the images for display.

Abstract: The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.