Abstract: An image sensor includes a substrate having first and second surfaces opposite to each other, an image pixel area, and a black level calibration (BLC) area adjacent to the image pixel area. The BLC area includes a dark current sensing circuit including photo diodes disposed in the substrate, a first seal ring disposed over the second surface and surrounding the image pixel area in plan view, a second seal ring disposed over the second surface and surrounding the image pixel area in plan view such that the dark current sensing circuit is disposed between the first and second seal rings, an opaque cover disposed over the first surface and covering the dark current sensing circuit, the first and second seal rings, and one or more first trench isolation structures extending from the first surface to an inside the substrate and disposed between the first seal ring and the opaque cover.

Abstract: An image sensor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a protection oxide film, and a nitride hard mask. The gate dielectric layer is over the semiconductor substrate. The gate electrode is over the gate dielectric layer. An entirety of a first portion of the gate dielectric layer directly under the gate electrode is of uniform thickness. The protection oxide film is in contact with a top surface of the gate electrode. The gate dielectric layer extends beyond a sidewall of the protection oxide film. The nitride hard mask is in contact with a top surface of the protection oxide film.

Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.

Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.

Abstract: A method of manufacturing a transistor structure includes forming a plurality of trenches in a substrate, lining the plurality of trenches with a dielectric material, forming first and second substrate regions at opposite sides of the plurality of trenches, and filling the plurality of trenches with a conductive material. The plurality of trenches includes first and second trenches aligned between the first and second substrate regions, and filling the plurality of trenches with the conductive material includes the conductive material extending continuously between the first and second trenches.

Abstract: A semiconductor structure includes a substrate having a pixel array region and a first seal ring region, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The semiconductor structure further includes a first isolation feature in the first seal ring region, wherein the first isolation feature is filled with a dielectric material, and the first isolation feature is a continuous structure surrounding the pixel array region. The semiconductor structure further includes a second isolation feature between the first isolation feature and the pixel array region, wherein the second isolation feature is filled with the dielectric material.

Abstract: A semiconductor structure includes a sensor chip. The sensor chip includes a pixel array region, a bonding pad region, and a periphery region surrounding the pixel array region. The semiconductor structure further includes a stress-releasing trench, wherein the stress-releasing trench is in the periphery region, and the stress-releasing trench fully surrounds a perimeter of the pixel array region and the bonding pad region.

Abstract: An IC structure includes a substrate region having a first doping type and including an upper surface, first and second regions within the substrate region, each of the first and second regions having a second doping type opposite the first doping type, and a gate conductor including a plurality of conductive protrusions extending into the substrate region in a direction perpendicular to a plane of the upper surface. The conductive protrusions are electrically connected to each other, and at least a portion of each conductive protrusion is positioned between the first and second regions.

Abstract: An image sensor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a protection oxide film, and a nitride hard mask. The gate dielectric layer is over the semiconductor substrate. The gate electrode is over the gate dielectric layer. An entirety of a first portion of the gate dielectric layer directly under the gate electrode is of uniform thickness. The protection oxide film is in contact with a top surface of the gate electrode. The gate dielectric layer extends beyond a sidewall of the protection oxide film. The nitride hard mask is in contact with a top surface of the protection oxide film.

Abstract: A method of detecting electromagnetic radiation includes illuminating a photodiode of a pixel sensor with electromagnetic radiation, using vertical gate structures of a transfer transistor to couple a cathode of the photodiode to an internal node of the pixel sensor, thereby generating an internal node voltage level, and generating an output voltage level of the pixel sensor based on the internal node voltage level.

Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.

Abstract: A semiconductor device includes a first wafer comprising a first portion of a seal ring structure within a body of the first wafer. The semiconductor device includes a second wafer comprising a second portion of the seal ring structure within a body of the second wafer. The second wafer is affixed to the first wafer such that the second portion of the seal ring structure is on the first portion of the seal ring structure. The semiconductor device includes a trench structure comprising a first trench in the first wafer and a second trench in the second wafer, where the first trench and the second trench are on a same side of the seal ring structure.

Abstract: A method includes depositing a gate dielectric layer over a substrate. A gate electrode layer, a protection oxide layer, and a hard mask are sequentially deposited over the gate dielectric layer. The gate electrode layer and the protection oxide layer are patterned by using the hard mask as an etching mask to form a gate structure over the gate dielectric layer. An etching process is performed to remove the hard mask and thin the protection oxide layer after forming the gate structure.

Abstract: A semiconductor structure includes a substrate having a pixel array region and a first seal ring region, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The semiconductor structure further includes a first isolation feature in the first seal ring region, wherein the first isolation feature is filled with a dielectric material, and the first isolation feature is a continuous structure surrounding the pixel array region. The semiconductor structure further includes a second isolation feature between the first isolation feature and the pixel array region, wherein the second isolation feature is filled with the dielectric material.

Abstract: A device including a semiconductive substrate having opposite first and second surfaces, a light-sensitive element in the semiconductive substrate, an isolation structure extending at least from the second surface of the semiconductive substrate to within the semiconductive substrate, and a color filter over the second surface of the semiconductive substrate. The isolation structure includes a dielectric fill and a first high-k dielectric layer wrapping around the dielectric fill.

Abstract: An IC structure includes a substrate region having a first doping type and including an upper surface, first and second regions within the substrate region, each of the first and second regions having a second doping type opposite the first doping type, and a gate conductor including a plurality of conductive protrusions extending into the substrate region in a direction perpendicular to a plane of the upper surface. The conductive protrusions are electrically connected to each other, and at least a portion of each conductive protrusion is positioned between the first and second regions.

Abstract: A semiconductor structure includes a sensor chip. The sensor chip includes a pixel array region, a bonding pad region, and a periphery region surrounding the pixel array region. The semiconductor structure further includes a stress-releasing trench, wherein the stress-releasing trench is in the periphery region, and the stress-releasing trench fully surrounds a perimeter of the pixel array region and the bonding pad region.

Abstract: A method includes depositing a gate dielectric layer over a substrate. A gate electrode layer, a protection oxide layer, and a hard mask are sequentially deposited over the gate dielectric layer. The gate electrode layer and the protection oxide layer are patterned by using the hard mask as an etching mask to form a gate structure over the gate dielectric layer. An etching process is performed to remove the hard mask and thin the protection oxide layer after forming the gate structure.

Abstract: A semiconductor structure includes a sensor wafer comprising a plurality of sensor chips on and within a substrate. Each of the plurality of sensor chips includes a pixel array region, a bonding pad region, and a periphery region. The periphery region is between adjacent to a scribe line, and the scribe line is between adjacent sensor chips of the plurality of sensor chips. Each of the plurality of sensor chips further includes a stress-releasing trench structure embedded in the substrate, wherein the stress-releasing trench structure is in the periphery region, and the stress-releasing trench structure fully surrounds a perimeter of the pixel array region and the bonding pad region of a corresponding sensor chip of the plurality of sensor chips.

Abstract: An image sensor includes a semiconductor substrate, a gate dielectric layer over the semiconductor substrate, a gate electrode over the gate dielectric layer, and a protection oxide film in contact with a top surface of the gate electrode. A top surface of the protection oxide film is free from contact with a hard mask comprising nitrogen.