Patents by Inventor Chun-Wei CHIA

Chun-Wei CHIA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200343282
    Abstract: A device including a semiconductive substrate having opposite first and second surfaces, a light-sensitive element in the semiconductive substrate, an isolation structure extending at least from the second surface of the semiconductive substrate to within the semiconductive substrate, and a color filter over the second surface of the semiconductive substrate. The isolation structure includes a dielectric fill and a first high-k dielectric layer wrapping around the dielectric fill.
    Type: Application
    Filed: July 11, 2020
    Publication date: October 29, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei CHENG, Chun-Wei CHIA, Chun-Hao CHOU, Kuo-Cheng LEE, Hsun-Ying HUANG
  • Patent number: 10714523
    Abstract: An optical isolation structure and a method for fabricating the same are provided. The optical isolation structure includes a first dielectric layer, a second dielectric layer, a third dielectric layer and a dielectric post. The first dielectric layer includes a trench portion located in a trench of the semiconductor substrate. The second dielectric layer includes a trench portion covering the trench portion of the first dielectric layer and located in the trench of the semiconductor substrate. The third dielectric layer includes a trench portion covering the trench portion of the second dielectric layer and located in the trench of the semiconductor substrate. The dielectric post is disposed in the trench of the semiconductor substrate and covering the trench portion of the third dielectric layer.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang
  • Publication number: 20200135789
    Abstract: A semiconductor structure includes a sensor wafer comprising a plurality of sensor chips on and within a substrate. Each of the plurality of sensor chips includes a pixel array region, a bonding pad region, and a periphery region. The periphery region is between adjacent to a scribe line, and the scribe line is between adjacent sensor chips of the plurality of sensor chips. Each of the plurality of sensor chips further includes a stress-releasing trench structure embedded in the substrate, wherein the stress-releasing trench structure is in the periphery region, and the stress-releasing trench structure fully surrounds a perimeter of the pixel array region and the bonding pad region of a corresponding sensor chip of the plurality of sensor chips.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 30, 2020
    Inventors: Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE, Ying-Hao CHEN, Chun-Wei CHIA
  • Publication number: 20190172870
    Abstract: An image sensor includes a semiconductor substrate, a gate dielectric layer over the semiconductor substrate, a gate electrode over the gate dielectric layer, and a protection oxide film in contact with a top surface of the gate electrode.
    Type: Application
    Filed: January 31, 2019
    Publication date: June 6, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei CHIA, Chun-Hao CHOU, Kai-Chun HSU, Kuo-Cheng LEE, Shyh-Fann TING
  • Publication number: 20190139998
    Abstract: An optical isolation structure and a method for fabricating the same are provided. The optical isolation structure includes a first dielectric layer, a second dielectric layer, a third dielectric layer and a dielectric post. The first dielectric layer includes a trench portion located in a trench of the semiconductor substrate. The second dielectric layer includes a trench portion covering the trench portion of the first dielectric layer and located in the trench of the semiconductor substrate. The third dielectric layer includes a trench portion covering the trench portion of the second dielectric layer and located in the trench of the semiconductor substrate. The dielectric post is disposed in the trench of the semiconductor substrate and covering the trench portion of the third dielectric layer.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei CHENG, Chun-Wei CHIA, Chun-Hao CHOU, Kuo-Cheng LEE, Hsun-Ying HUANG
  • Patent number: 10204960
    Abstract: A method of fabricating polysilicon gate structure in an image sensor device includes depositing a gate dielectric layer on a surface of a substrate. Then a polysilicon layer is deposited over the gate dielectric layer. Next, a protection film is deposited over the polysilicon layer. A hard mask is formed over the protection film, and the polysilicon gate structure is patterned. Following that, the hard mask is stripped off. The protection film exhibits etching selectivity against the polysilicon layer and has a thickness of between 40 and 60 angstroms. The hard mask is removed by phosphoric acid solution wet etching process.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei Chia, Chun-Hao Chou, Kai-Chun Hsu, Kuo-Cheng Lee, Shyh-Fann Ting
  • Patent number: 10157949
    Abstract: An optical isolation structure and a method for fabricating the same are provided. The optical isolation structure includes a first dielectric layer, a second dielectric layer, a third dielectric layer and a dielectric post. The first dielectric layer includes a trench portion located in a trench of the semiconductor substrate. The second dielectric layer includes a trench portion covering the trench portion of the first dielectric layer and located in the trench of the semiconductor substrate. The third dielectric layer includes a trench portion covering the trench portion of the second dielectric layer and located in the trench of the semiconductor substrate. The dielectric post is disposed in the trench of the semiconductor substrate and covering the trench portion of the third dielectric layer.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang
  • Publication number: 20180269237
    Abstract: An optical isolation structure and a method for fabricating the same are provided. The optical isolation structure includes a first dielectric layer, a second dielectric layer, a third dielectric layer and a dielectric post. The first dielectric layer includes a trench portion located in a trench of the semiconductor substrate. The second dielectric layer includes a trench portion covering the trench portion of the first dielectric layer and located in the trench of the semiconductor substrate. The third dielectric layer includes a trench portion covering the trench portion of the second dielectric layer and located in the trench of the semiconductor substrate. The dielectric post is disposed in the trench of the semiconductor substrate and covering the trench portion of the third dielectric layer.
    Type: Application
    Filed: March 14, 2017
    Publication date: September 20, 2018
    Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang
  • Publication number: 20170084664
    Abstract: A method of fabricating polysilicon gate structure in an image sensor device includes depositing a gate dielectric layer on a surface of a substrate. Then a polysilicon layer is deposited over the gate dielectric layer. Next, a protection film is deposited over the polysilicon layer. A hard mask is formed over the protection film, and the polysilicon gate structure is patterned. Following that, the hard mask is stripped off. The protection film exhibits etching selectivity against the polysilicon layer and has a thickness of between 40 and 60 angstroms. The hard mask is removed by phosphoric acid solution wet etching process.
    Type: Application
    Filed: September 17, 2015
    Publication date: March 23, 2017
    Inventors: Chun-Wei CHIA, Chun-Hao CHOU, Kai-Chun HSU, Kuo-Cheng LEE, Shyh-Fann TING