Patents by Inventor Chun-Wen Cheng

Chun-Wen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210365398
    Abstract: In one example, an adapter card may include a circuit board having a male interface to be inserted into a discrete graphics card slot and a peripheral component interconnect express (PCIe) slot to communicatively couple a PCIe device. Further, the adapter card may include a voltage converter circuit disposed on the circuit board to convert a first voltage associated with the discrete graphics card slot to a second voltage corresponding to the PCIe device and a level shifter circuit disposed on the circuit board to modify a signal level in the discrete graphics card slot to a signal level in the PCIe device.
    Type: Application
    Filed: October 23, 2018
    Publication date: November 25, 2021
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Po-Ying Chih, Chao-Wen Cheng, Chun-Yi Liu
  • Patent number: 11184694
    Abstract: An integrated microphone device is provided. The integrated microphone device includes a substrate, a plate, and a membrane. The substrate includes an aperture allowing acoustic pressure to pass through. The plate is disposed on a side of the substrate. The membrane is disposed between the substrate and the plate and movable relative to the plate as acoustic pressure strikes the membrane. The membrane includes a vent valve having an open area that is variable in response to a change in acoustic pressure.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Chun-Yin Tsai, Tzu-Heng Wu, Wen-Cheng Kuo
  • Patent number: 11180363
    Abstract: A MEMS support structure and a cap structure are provided. At least one vertically-extending trench is formed into the MEMS support structure or a portion of the cap structure. A vertically-extending outgassing material portion having a surface that is physically exposed to a respective vertically-extending cavity is formed in each of the at least one vertically-extending trench. A matrix material layer is attached to the MEMS support structure. A movable element laterally confined within a matrix layer is formed by patterning the matrix material layer. The matrix layer is bonded to the cap structure. A sealed chamber containing the movable element is formed. Each vertically-extending outgassing material portion has a surface that is physically exposed to the sealed chamber, and outgases a gas to increase the pressure in the sealed chamber.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuei-Sung Chang, Tai-Bang An, Chun-wen Cheng, Hung-Hua Lin
  • Patent number: 11174158
    Abstract: In some embodiments, a sensor is provided. The sensor includes a microelectromechanical systems (MEMS) substrate disposed over an integrated chip (IC), where the IC defines a lower portion of a first cavity and a lower portion of a second cavity, and where the first cavity has a first operating pressure different than an operating pressure of the second cavity. A cap substrate is disposed over the MEMS substrate, where a first pair of sidewalls of the cap substrate partially define an upper portion of the first cavity, and a second pair of sidewalls of the cap substrate partially define an upper portion of the second cavity. A sensor area comprising a movable portion of the MEMS substrate and a dummy area comprising a fixed portion of the MEMS substrate are both disposed in the first cavity. A pressure enhancement structure is disposed in the dummy area.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Fei-Lung Lai, Kuei-Sung Chang, Shang-Ying Tsai
  • Patent number: 11171285
    Abstract: Provided is a non-ferromagnetic spacing composite layer, comprising first, second and third spacing layers stacked in sequence. The first and third spacing layers are each made of Re, Rh, Ir, W, Mo, Ta, or Nb, and the second spacing layer is made of Ru. The second spacing layer has a thickness of equal to or more than 0.18 nm, and the non-ferromagnetic spacing composite layer has a total thickness of 0.6 nm to 1 nm. Also, provided are a method of preparing the non-ferromagnetic spacing composite layer, a synthetic antiferromagnetic laminated structure, and an MRAM. The synthetic antiferromagnetic laminated structure can maintain a certain coupling strength and the RKKY indirect interaction after thermal treatment, thereby keeping the recording function of MRAM.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 9, 2021
    Assignee: SOLAR APPLIED MATERIALS TECHNOLOGY CORP.
    Inventors: Chih-Huang Lai, Chun-Liang Yang, Yi-Huan Chung, Wei-Chih Huang, Chih-Wen Tang, Hui-Wen Cheng
  • Patent number: 11152338
    Abstract: A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Qiang Wu, Chun-Fu Cheng, Chung-Cheng Wu, Yi-Han Wang, Chia-Wen Liu
  • Patent number: 11150561
    Abstract: A method for collecting information in image-error compensation is provided. The method includes providing a reticle having a first image structure and a second image structure; moving a light shading member to control a first exposure field; projecting a light over the first exposure field; recording an image of the first image structure after the light is projected; moving the light shading member to control a second exposure field; projecting the light over the second exposure field; and recording an image of the second image structure after the light is projected.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
  • Publication number: 20210314707
    Abstract: A MEMS microphone includes a substrate having an opening, a first diaphragm, a first backplate, a second diaphragm, and a backplate. The first diaphragm faces the opening in the substrate. The first backplate includes multiple accommodating-openings and it is spaced apart from the first diaphragm. The second diaphragm joints the first diaphragm together at multiple locations by pillars passing through the accommodating-openings in the first backplate. The first backplate is located between the first diaphragm and the second diaphragm. The second backplate includes at least one vent hole and it is spaced apart from the second diaphragm. The second diaphragm is located between the first backplate and the second backplate.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 7, 2021
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Wen-Tuan Lo
  • Publication number: 20210309508
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.
    Type: Application
    Filed: June 16, 2021
    Publication date: October 7, 2021
    Inventors: Kuei-Sung Chang, Chun-Wen Cheng, Fei-Lung Lai, Shing-Chyang Pan, Yuan-Chih Hsieh, Yi-Ren Wang
  • Publication number: 20210305376
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate. The silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer is thinner than the second metal-containing layer.
    Type: Application
    Filed: June 11, 2021
    Publication date: September 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Wen TSAU, Chun-I WU, Ziwei FANG, Huang-Lin CHAO, I-Ming CHANG, Chung-Liang CHENG, Chih-Cheng LIN
  • Publication number: 20210302367
    Abstract: A biochip including a fluidic substrate having an opening extending completely through the fluidic substrate. The biochip further includes a silicon oxide coating on the fluidic substrate. The biochip further includes a plurality of sidewalls on the fluidic substrate, wherein the plurality of sidewalls defines a channel in fluid communication with the opening, the silicon oxide coating is between adjacent sidewalls of the plurality of sidewalls, and each of the plurality of sidewalls comprises polydimethylsiloxane (PDMS). The biochip further includes a detection substrate spaced from the fluidic substrate.
    Type: Application
    Filed: April 2, 2021
    Publication date: September 30, 2021
    Inventors: Yi-Shao LIU, Chun-Ren CHENG, Chun-wen CHENG
  • Publication number: 20210296168
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng
  • Publication number: 20210296303
    Abstract: A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.
    Type: Application
    Filed: May 26, 2021
    Publication date: September 23, 2021
    Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
  • Patent number: 11117796
    Abstract: An embodiment is a MEMS device including a first MEMS die having a first cavity at a first pressure, a second MEMS die having a second cavity at a second pressure, the second pressure being different from the first pressure, and a molding material surrounding the first MEMS die and the second MEMS die, the molding material having a first surface over the first and the second MEMS dies. The device further includes a first set of electrical connectors in the molding material, each of the first set of electrical connectors coupling at least one of the first and the second MEMS dies to the first surface of the molding material, and a second set of electrical connectors over the first surface of the molding material, each of the second set of electrical connectors being coupled to at least one of the first set of electrical connectors.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Jung-Huei Peng, Shang-Ying Tsai, Hung-Chia Tsai, Yi-Chuan Teng
  • Patent number: 11107630
    Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Patent number: 11099152
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: August 24, 2021
    Inventors: Yi-Shao Liu, Chun-Ren Cheng, Ching-Ray Chen, Yi-Hsien Chang, Fei-Lung Lai, Chun-Wen Cheng
  • Publication number: 20210246014
    Abstract: A MEMS support structure and a cap structure are provided. At least one vertically-extending trench is formed into the MEMS support structure or a portion of the cap structure. A vertically-extending outgassing material portion having a surface that is physically exposed to a respective vertically-extending cavity is formed in each of the at least one vertically-extending trench. A matrix material layer is attached to the MEMS support structure. A movable element laterally confined within a matrix layer is formed by patterning the matrix material layer. The matrix layer is bonded to the cap structure. A sealed chamber containing the movable element is formed. Each vertically-extending outgassing material portion has a surface that is physically exposed to the sealed chamber, and outgases a gas to increase the pressure in the sealed chamber.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 12, 2021
    Inventors: Kuei-Sung Chang, Tai-Bang An, Chun-wen Cheng, Hung-Hua Lin
  • Patent number: 11089408
    Abstract: A MEMS microphone includes a backplate that has a plurality of open areas, and a diaphragm spaced apart from the backplate. The diaphragm is deformable by sound waves to cause gaps between the backplate and the diaphragm being changed at multiple locations on the diaphragm. The diaphragm includes a plurality of anchor areas, located near a boundary of the diaphragm, which is fixed relative to the backplate. The diaphragm also includes multiple vent valves. Examples of the vent valve include a wing vent valve and a vortex vent valve.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Chun Yin Tsai
  • Publication number: 20210238030
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a microelectromechanical systems (MEMS) device. The method includes forming a filter stack over a carrier substrate. The filter stack comprises a particle filter layer having a particle filter. A support structure layer is formed over the filter stack. The support structure layer is patterned to define a support structure in the support structure layer such that the support structure has one or more segments. The support structure is bonded to a MEMS structure.
    Type: Application
    Filed: March 31, 2021
    Publication date: August 5, 2021
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Wen Cheng Kuo
  • Patent number: 11078074
    Abstract: Processes for integrating complementary metal-oxide-semiconductor (CMOS) devices with microelectromechanical systems (MEMS) devices are provided. In some embodiments, the MEMS devices are formed on a sacrificial substrate or wafer, the sacrificial substrate or wafer is bonded to a CMOS die or wafer, and the sacrificial substrate or wafer is removed. In other embodiments, the MEMS devices are formed over a sacrificial region of a CMOS die or wafer and the sacrificial region is subsequently removed. Integrated circuit (ICs) resulting from the processes are also provided.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu