Patents by Inventor Chun-Wen Cheng
Chun-Wen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11678133Abstract: The present disclosure provides one embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate. A silicon oxide layer formed on one side of the first silicon substrate. A second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates. A diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates such that the first plate and the diaphragm are configured to form a capacitive microphone.Type: GrantFiled: September 14, 2020Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Huei Peng, Chia-Hua Chu, Chun-Wen Cheng, Chin-Yi Cho, Li-Min Hung, Yao-Te Huang
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Patent number: 11667517Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.Type: GrantFiled: June 22, 2020Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng
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Patent number: 11661333Abstract: A semiconductor structure includes a substrate; a sensing device disposed over the substrate and including a plurality of protruding members protruded from the sensing device; a sensing structure disposed adjacent to the sensing device and including a plurality of sensing electrodes protruded from the sensing structure towards the sensing device; and an actuating structure disposed adjacent to the sensing device and configured to provide an electrostatic force on the sensing device based on a feedback from the sensing structure. Further, a method of manufacturing the semiconductor structure is also disclosed.Type: GrantFiled: October 14, 2020Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Jhih Mao, Shang-Ying Tsai, Kuei-Sung Chang, Chun-Wen Cheng
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Patent number: 11649162Abstract: Various embodiments of the present disclosure are directed towards a method for manufacturing a microelectromechanical systems (MEMS) device. The method includes forming a particle filter layer over a carrier substrate. The particle filter layer is patterned while the particle filter layer is disposed on the carrier substrate to define a particle filter in the particle filter layer. A MEMS substrate is bonded to the carrier substrate. A MEMS structure is formed over the MEMS substrate.Type: GrantFiled: March 5, 2021Date of Patent: May 16, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hua Chu, Chun-Wen Cheng, Wen Cheng Kuo
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Publication number: 20230081170Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.Type: ApplicationFiled: October 31, 2022Publication date: March 16, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Alexander KALNITSKY, Yi-Shao LIU, Kai-Chih LIANG, Chia-Hua CHU, Chun-Ren CHENG, Chun-Wen CHENG
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Patent number: 11581476Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first piezoelectric layer, and a first dummy layer. The first piezoelectric layer is over the substrate, and the first piezoelectric layer has a first top surface. The first dummy layer is over the first piezoelectric layer, and the first dummy layer has a second top surface. And an average roughness of the first top surface is greater than an average roughness of the second top surface. A method for manufacturing the semiconductor structure is also provided.Type: GrantFiled: March 13, 2020Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Wen Cheng, Chun Yin Tsai, Chia-Hua Chu
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Patent number: 11577954Abstract: A method for forming a MEMS device includes following operations. A first semiconductor layer is formed over a substrate. A plurality of first pillars are formed over the first layer. A second layer is formed over the first pillars and the first layer. A plurality of second pillars are formed over the second layer. A third layer is formed over the second pillars and the second layer.Type: GrantFiled: December 7, 2020Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen Hsiung Yang, Chun-Wen Cheng, Chia-Hua Chu, En-Chan Chen
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Publication number: 20220415699Abstract: Disclosed is a vacuum chuck and a method for securing a warped semiconductor substrate during a semiconductor manufacturing process so as to improve its flatness during a semiconductor manufacturing process. For example, a semiconductor manufacturing system includes: a vacuum chuck configured to hold a substrate, wherein the vacuum chuck comprises, a plurality of vacuum grooves located on a top surface of the vacuum chuck, wherein the top surface is configured to face the substrate; and a plurality of flexible seal rings disposed on the vacuum chuck and extending outwardly from the top surface, wherein the plurality of flexible seal rings are configured to directly contact a bottom surface of the substrate and in adjacent to the plurality of vacuum grooves so as to form a vacuum seal between the substrate and the vacuum chuck, and wherein each of the plurality of flexible seal rings has a zigzag cross section.Type: ApplicationFiled: August 8, 2022Publication date: December 29, 2022Inventors: Chien-Fa LEE, Chin-Lin CHOU, Shang-Ying TSAI, Shou-Wen KUO, Kuei-Sung CHANG, Jiun-Rong PAI, Hsu-Shui LIU, Chun-Wen CHENG
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Patent number: 11533565Abstract: A MEMS microphone includes a substrate having an opening, a first diaphragm, a first backplate, a second diaphragm, and a backplate. The first diaphragm faces the opening in the substrate. The first backplate includes multiple accommodating-openings and it is spaced apart from the first diaphragm. The second diaphragm joints the first diaphragm together at multiple locations by pillars passing through the accommodating-openings in the first backplate. The first backplate is located between the first diaphragm and the second diaphragm. The second backplate includes at least one vent hole and it is spaced apart from the second diaphragm. The second diaphragm is located between the first backplate and the second backplate.Type: GrantFiled: June 17, 2021Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wen Cheng, Chia-Hua Chu, Wen-Tuan Lo
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Publication number: 20220380208Abstract: A stacked semiconductor structure includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Chia-Hua Chu, Chun-Wen Cheng
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Patent number: 11505454Abstract: A method for manufacturing a MEMS structure is provided. The method includes providing a MEMS substrate having a first surface, forming a first buffer layer on the first surface of the MEMS substrate, and forming a first roughening layer on the first buffer layer. Also, a MEMS structure is provided. The MEMS structure includes a MEMS substrate, a first buffer layer, a first roughening layer, and a CMOS substrate. The MEMS substrate has a first surface and a pillar is on the first surface. The first buffer layer is on the first surface. The first roughening layer is on the first buffer layer. The CMOS substrate has a second surface and is bonded to the MEMS substrate via the pillar. Moreover, an air gap is between the first roughening layer and the second surface of the CMOS substrate.Type: GrantFiled: September 25, 2019Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kang-Che Huang, Yi-Chien Wu, Shiang-Chi Lin, Jung-Huei Peng, Chun-Wen Cheng
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Patent number: 11508608Abstract: Disclosed is a vacuum chuck and a method for securing a warped semiconductor substrate during a semiconductor manufacturing process so as to improve its flatness during a semiconductor manufacturing process. For example, a semiconductor manufacturing system includes: a vacuum chuck configured to hold a substrate, wherein the vacuum chuck comprises, a plurality of vacuum grooves located on a top surface of the vacuum chuck, wherein the top surface is configured to face the substrate; and a plurality of flexible seal rings disposed on the vacuum chuck and extending outwardly from the top surface, wherein the plurality of flexible seal rings are configured to directly contact a bottom surface of the substrate and in adjacent to the plurality of vacuum grooves so as to form a vacuum seal between the substrate and the vacuum chuck, and wherein each of the plurality of flexible seal rings has a zigzag cross section.Type: GrantFiled: August 20, 2020Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Fa Lee, Chin-Lin Chou, Shang-Ying Tsai, Shou-Wen Kuo, Kuei-Sung Chang, Jiun-Rong Pai, Hsu-Shui Liu, Chun-wen Cheng
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Publication number: 20220369041Abstract: A MEMS device and a method of manufacturing the same are provided. A semiconductor device includes a substrate; and a membrane over the substrate and configured to generate charges in response to an acoustic wave, the membrane being in a polygonal shape including vertices. The membrane includes a via pattern having first lines that partition the membrane into slices and extend to the vertices of the membrane such that the slices are separated from each other near an anchored region of the membrane and connected to each other around a central region. The via pattern further includes second lines extending from the anchored region of the membrane toward the central region of the membrane. Each of the second lines includes a length less than a length of each of the first lines.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: CHUN-WEN CHENG, CHUN YIN TSAI, CHIA-HUA CHU
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Patent number: 11498832Abstract: A stacked semiconductor structure includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units.Type: GrantFiled: May 21, 2018Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hua Chu, Chun-Wen Cheng
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Patent number: 11486854Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.Type: GrantFiled: December 26, 2019Date of Patent: November 1, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Alexander Kalnitsky, Yi-Shao Liu, Kai-Chih Liang, Chia-Hua Chu, Chun-Ren Cheng, Chun-Wen Cheng
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Publication number: 20220333251Abstract: The present disclosure provides a gas sensor. The gas sensor includes a substrate, a conductor layer over the substrate, wherein the conductor layer includes a conductive pattern including a plurality of openings, the openings being arranged in a repeating pattern, an insulating layer in the plurality of openings and over a top surface of the conductive pattern, wherein the conductive pattern is embedded in the insulating layer, and a gas sensing film over a portion of the insulating layer.Type: ApplicationFiled: June 20, 2022Publication date: October 20, 2022Inventors: MING-TA LEI, CHIA-HUA CHU, HSIN-CHIH CHIANG, TUNG-TSUN CHEN, CHUN-WEN CHENG
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Publication number: 20220315414Abstract: The present disclosure provides a semiconductor structure and a method for fabricating semiconductor structure. The semiconductor structure includes a first device, configured to be a complementary metal oxide semiconductor device, wherein the first device includes a substrate, a multi-layer structure disposed on the substrate, a first hole, defined between a first end with a first circumference and a second end with a second circumference, a second hole, aligned to the first hole and defined between the second end and a third end with a third circumference, wherein the third circumference is larger than the first circumference and the second circumference, and a second device, configured to be a micro-electro mechanical system device and bonded to the first device, wherein a first chamber is between the first device and the second device, and the first end links with the first chamber, and a sealing object configured to seal the second hole.Type: ApplicationFiled: June 24, 2022Publication date: October 6, 2022Inventors: CHUN-WEN CHENG, YI-CHUAN TENG, CHENG-YU HSIEH, LEE-CHUAN TSENG, SHIH-CHANG LIU, SHIH-WEI LIN
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Publication number: 20220289556Abstract: Various embodiments of the present disclosure are directed towards an electronic device that comprises a semiconductor substrate having a first surface opposite a second surface. The semiconductor substrate at least partially defines a cavity. A first microelectromechanical systems (MEMS) device is disposed along the first surface of the semiconductor substrate. The first MEMS device comprises a first backplate and a diaphragm vertically separated from the first backplate. A second MEMS device is disposed along the first surface of the semiconductor substrate. The second MEMS device comprises spring structures and a moveable element. The spring structures are configured to suspend the moveable element in the cavity. A segment of the semiconductor substrate continuously laterally extends from under a sidewall of the first MEMS device to under a sidewall of the second MEMS device.Type: ApplicationFiled: June 21, 2021Publication date: September 15, 2022Inventors: Chun-Wen Cheng, Chia-Hua Chu, Chun Yin Tsai, Wen Cheng Kuo
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Patent number: 11434129Abstract: A semiconductor structure includes: a first device; a second device contacted with the first device, wherein a chamber is formed between the first device and the second device; a first hole disposed in the second device and defined between a first end with a first circumference and a second end with a second circumference; a second hole disposed in the second device and aligned to the first hole; and a sealing object for sealing the second hole. The first end links with the chamber, and the first circumference is different from the second circumference, the second hole is defined between the second end and a third end with a third circumference, and the second circumference and the third circumference are smaller than the first circumference.Type: GrantFiled: January 17, 2017Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Wen Cheng, Yi-Chuan Teng, Cheng-Yu Hsieh, Lee-Chuan Tseng, Shih-Chang Liu, Shih-Wei Lin
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Patent number: 11418887Abstract: A MEMS device and a method of manufacturing the same are provided. A semiconductor device includes a substrate and a membrane over the substrate. The membrane includes a piezoelectric material configured to generate charges in response to an acoustic wave. The membrane includes a via pattern having first lines that partition the membrane into slices such that the slices are separated from each other at a first region near an edge of the membrane and connected to each other at a second region.Type: GrantFiled: June 18, 2020Date of Patent: August 16, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Wen Cheng, Chun Yin Tsai, Chia-Hua Chu