Abstract: A multi-state indicator comprises a voltage generator, for generating M voltages, with M being an integer larger than 3; and a multi-state detector, coupled to the voltage generator, for receiving M voltages, having a voltage input end for receiving an input voltage to generate an indication signal whereby the indication signal is capable of indicating the input voltage with reference to the M voltages. Unlike the prior art, a multi-state detector having level shifters according to the present invention alleviates problems of static currents and over-large areas for circuits implementing typical differential comparators.

Abstract: A transmitter comprises a protection circuit; a first termination resistor having a first end coupled to a first voltage source, and a second end coupled to the protection circuit; a second termination resistor having a first end coupled to the first voltage source, and a second end coupled to the protection circuit, wherein the second end of the first termination resistor and the second end of the second termination resistor form a differential output pair; a current switch coupled to the protection circuit; a current source coupled to the current switch; and a pre-driver circuit coupled to the current switch, for controlling the current switch, making the differential output pair generate an output current. Wherein, the pre-driver circuit receives a second voltage source, and the first voltage source is higher than the second voltage source.

Abstract: A multi-mode output transmitter includes a pair of driving circuits and a pair of common circuits. Each of the driving circuits includes an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET), and each of the common circuits includes a p-channel MOSFET. In one transmission mode, one of the pair of common circuits and one of the pair of driving circuits complementarily conduct; and in another transmission mode, the pair of common circuits simultaneously conduct to provide termination resistors.

Abstract: A protection circuit for an NMOS device is provided. The protection circuit includes a cascoding NMOS transistor and an adjusting circuit. The cascoding NMOS transistor is cascoded between the NMOS device and an external voltage source. The adjusting circuit is coupled to the external voltage source, a gate of the cascoding NMOS transistor, and an internal voltage source. The adjusting circuit adjusts the voltage at the gate of the cascoding NMOS transistor according to the voltages of the external voltage source and the internal voltage source so as to protect the NMOS device from a voltage stress caused by the external voltage source.

Abstract: A display controller, video signal transmitting method and system thereof are provided. The display controller includes a processing circuit; a transmitting channel, coupled to the processing circuit; a receiving channel, coupled to the processing circuit; and a clock generator, that generates an internal clock signal and an external clock signal. Upon receiving a video signal, the processing circuit processes a first partial pixel data of the video signal to output a first display control signal. The transmitting channel converts a second partial pixel data of the video signal to a partial video signal having a multiple data rate according to the internal clock signal to be outputted.

Abstract: A test system for testing operability of integrated circuits includes: a first IC, for modulating a first signal to generate a first modulated signal and transmitting the first modulated signal, and for receiving a second modulated signal and demodulating the second modulated signal to generate a second signal; a first loop antenna, coupled to the first IC, for receiving the first modulated signal and sending the first modulated signal back to the first IC as the second modulated signal; and a tester circuit coupled to the first IC, for generating the first signal to the first IC, receiving the second signal from the first IC, and comparing the first signal and the second signal to determine the operability of the first IC.

Abstract: A variable-frequency network connection establishing method is adapted for establishing a connection between a local network device and a remote network device. The variable-frequency network connection establishing method includes the steps of: providing a plurality of local communications protocols including a local standard communications protocol and a local variable-frequency communications protocol to the remote network device; receiving a remote communications protocol provided by the remote network device; generating an indicator signal in accordance with the remote communications protocol and the plurality of local communications protocols; and operating in one of a standard mode and variable-frequency mode according to the indicator signal.

Abstract: A remote control method for a local physical layer device includes receiving a received packet, determining a coding of the received packet according to a packet format to generate a first determining result, determining an identification of the received packet according to the packet format to generate a second determining result, discarding the received packet according to the first determining result and the second determining result or decoding the received packet according to the packet format to generate a decoding result, and controlling or negotiating with a remote physical layer device according the decoding result.

Abstract: A network communications device is capable of promoting connection quality, and includes: a plurality of transmitting units for outputting a plurality of analog transmit-signals to another network communications device based on a plurality of digital transmit-signals; a plurality of receiving units for outputting a plurality of digital receive-signals based on a plurality of analog receive-signals sent from the another network communications device; an echo canceller for providing a signal for canceling an echo in one of the digital receive-signals; a near end crosstalk canceller for providing a signal for canceling near end crosstalk in one of the digital receive-signals; a decoding circuit for generating a decoded signal based on one of the digital receive-signals subsequent to cancellation of the echo and the near end crosstalk therein; and a power-increasing control circuit for increasing operating power so as to promote connection quality.

Abstract: A communications device is capable of adjusting power consumed thereby and includes a receiver and a control circuit. The receiver includes an analog-to-digital converter and a decoding circuit. The analog-to-digital converter receives receive-data from another communications device, converts the receive-data into a digital signal, and provides the digital signal to the decoding circuit for decoding. Based on the digital signal, the control circuit obtains a signaling index that indicates a communications quality of the receiver. The control circuit determines an operating state of the analog-to-digital converter and the decoding circuit in accordance with the signaling index and a receiving index. When the signaling index conforms with a reference range, the control circuit reduces a reference signal so as to reduce linearity of the analog-to-digital converter in accordance with the receiving index, and reduces a decoding capability of the decoding circuit in accordance with the receiving index.

Abstract: A test system for testing operability of integrated circuits includes: a first IC, for modulating a first signal to generate a first modulated signal and transmitting the first modulated signal, and for receiving a second modulated signal and demodulating the second modulated signal to generate a second signal; a first loop antenna, coupled to the first IC, for receiving the first modulated signal and sending the first modulated signal back to the first IC as the second modulated signal; and a tester circuit coupled to the first IC, for generating the first signal to the first IC, receiving the second signal from the first IC, and comparing the first signal and the second signal to determine the operability of the first IC.

Abstract: A protection circuit for an NMOS device is provided. The protection circuit includes a cascoding NMOS transistor and an adjusting circuit. The cascoding NMOS transistor is cascoded between the NMOS device and an external voltage source. The adjusting circuit is coupled to the external voltage source, a gate of the cascoding NMOS transistor, and an internal voltage source. The adjusting circuit adjusts the voltage at the gate of the cascoding NMOS transistor according to the voltages of the external voltage source and the internal voltage source so as to protect the NMOS device from a voltage stress caused by the external voltage source.

Abstract: A dynamic slew rate controlling method and a device is provided to reduce SSO variance generated from voltage noises, which is as a result of a plurality of data bits switching to the same state simultaneously while the I/O bus transmits these data bits. The device and method at first analyzes data patterns, then determines the slew rate controlling setting value based on the slew rate controlling mapping table corresponding to different data patterns, and then transmits the setting value to the I/O buffer with the same voltage level in order to reduce the SSO variance.

Abstract: A pulse duty cycle automatic correction device has a pulse width detector for detecting the high, low level pulse widths of the input cycle pulse so as to generate high, low level signals; a comparator encoder for comparing the high, low level signals, calculating out a correction delay time, and generating a correction delay signal and an output selection signal; a delay circuit for generating a delay cycle pulse; a compensation circuit for compensating the input cycle pulse so as to generate an input compensation pulse; a logic circuit for generating two cycle pulses according to the delay cycle pulse and the input compensation pulse; and a multiplexer for receiving the two cycle pulses and the input cycle pulse, and generating the output cycle pulse with duty cycle of 50% according to the output selection signal.

Abstract: A dynamic slew rate controlling method and a device is provided to reduce SSO variance generated from voltage noises, which is as a result of a plurality of data bits switching to the same state simultaneously while the I/O bus transmits these data bits. The device and method at first analyzes data patterns, then determines the slew rate controlling setting value based on the slew rate controlling mapping table corresponding to different data patterns, and then transmits the setting value to the I/O buffer with the same voltage level in order to reduce the SSO variance.