Patents by Inventor Chun-Yao Yang
Chun-Yao Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9966434Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.Type: GrantFiled: June 26, 2017Date of Patent: May 8, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Yi-Wei Chen, I-Cheng Hu, Yu-Shu Lin, Neng-Hui Yang
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Publication number: 20180108570Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.Type: ApplicationFiled: November 19, 2017Publication date: April 19, 2018Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
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Patent number: 9947588Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.Type: GrantFiled: November 19, 2017Date of Patent: April 17, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
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Patent number: 9929264Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.Type: GrantFiled: June 20, 2017Date of Patent: March 27, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
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Patent number: 9859164Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.Type: GrantFiled: October 17, 2016Date of Patent: January 2, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
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Publication number: 20170365703Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.Type: ApplicationFiled: June 20, 2017Publication date: December 21, 2017Inventors: Yu-Ying LIN, Kuan Hsuan KU, I-Cheng HU, Chueh-Yang LIU, Shui-Yen LU, Yu Shu LIN, Chun Yao YANG, Yu-Ren WANG, Neng-Hui YANG
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Patent number: 9842760Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate having a fin-shaped structure thereon is provided, a spacer is formed adjacent to the fin-shaped structure, and the spacer is used as mask to remove part of the substrate for forming an isolation trench, in which the isolation trench includes two sidewall portions and a bottom portion. Next, a plasma doping process is conducted to implant dopants into the two sidewall portions and the bottom portion of the isolation trench.Type: GrantFiled: July 20, 2016Date of Patent: December 12, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Tong-Jyun Huang, Shih-Hung Tsai, Jyh-Shyang Jenq, Chun-Yao Yang, Ming-Shiou Hsieh, Rong-Sin Lin
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Publication number: 20170330937Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.Type: ApplicationFiled: June 26, 2017Publication date: November 16, 2017Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Yi-Wei Chen, I-Cheng Hu, Yu-Shu Lin, Neng-Hui Yang
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Patent number: 9722030Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.Type: GrantFiled: June 7, 2016Date of Patent: August 1, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Yi-Wei Chen, I-Cheng Hu, Yu-Shu Lin, Neng-Hui Yang
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Patent number: 9716165Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.Type: GrantFiled: June 21, 2016Date of Patent: July 25, 2017Assignee: United Microelectronics CorporationInventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
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Patent number: 9609414Abstract: An earphone with at least one air orifice contains a body. The body includes at least one slot defined on a rear cap thereof, and each of the at least one slot has at least one air orifice formed therein. Thereby, the air discharges or draws to vibrate the speaker via the at least one air orifice to reduce resistance of the air against the speaker and to enhance tone quality, when the speaker vibrates in a closed space.Type: GrantFiled: December 2, 2014Date of Patent: March 28, 2017Assignee: M2 Technology, Inc.Inventor: Chun-Yao Yang
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Patent number: 9543408Abstract: A method of forming a patterned hark mask layer includes the following steps. A semiconductor substrate is provided. An amorphous silicon layer is formed on the semiconductor substrate. An implantation process is performed on the amorphous silicon layer. An annealing treatment is performed on the amorphous silicon layer after the implantation process. A patterned hard mask layer is formed on the amorphous silicon layer after the annealing treatment.Type: GrantFiled: August 26, 2015Date of Patent: January 10, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Hui Lin, Keng-Jen Lin, Chun-Yao Yang, Yu-Ren Wang
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Publication number: 20160360308Abstract: A push-pull earphone contains: a front cover, a closing sleeve, a first speaker element, and a second speaker element. The closing sleeve is mounted on the front cover, and the first speaker element and the second speaker element are fixed in the closing sleeve. Thereby, the first speaker element is fixed opposite to the second speaker element in the closing sleeve in an air-tight connecting manner or in other joining manners. In operation, the first speaker element and the second speaker element are “pushed” and “pulled” simultaneously to reduce nonlinear distortion caused by offset, when a vibration diaphragm of a loudspeaker operates, thus reproducing resolution, increasing high sensitivity (S/N ratio) and efficiency (db value). Accordingly, the push-pull earphone achieves brilliant frequency response and sensitivity to maintain quality (high C/P value), while playing music at bass.Type: ApplicationFiled: June 3, 2015Publication date: December 8, 2016Inventor: Chun-Yao Yang
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Patent number: 9437987Abstract: A connecting structure for an earphone contains: a male connector and a female connector. The male connector includes a plug terminal and an insulation holder, the plug terminal has a locking portion adjacent to a bottom of the plug terminal, and the plug terminal has at least one protrusion extending outwardly from a peripheral side of the locking portion. The plug terminal is mounted in the insulation holder, and between the insulation holder and the plug terminal is defined an inserting groove. The female connector includes an insertion seat and a body. The body has a fixing portion inserted into the inserting groove, and the fixing portion has at least one alignment orifice corresponding to the at least one protrusion. The insertion seat is fixed in the body to electrically connect with the plug terminal.Type: GrantFiled: July 9, 2015Date of Patent: September 6, 2016Assignee: M2 Technology, Inc.Inventor: Chun-Yao Yang
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Patent number: 9380375Abstract: An earphone with a speaker ring contains: a sound guiding tube, a speaker, and a body. The sound guiding tube is connected with the body, and the speaker is disposed in the sound guiding tube. The speaker has a first O ring fitted on a front end thereof and a second O ring fitted on a rear end thereof, and the first O ring and the second O ring are defined between the speaker and the sound guiding tube. Thereby, the first O ring, the second O ring, and the third O ring are arranged between the speaker and the sound guiding tube to reduce the resistance between the speaker and the sound guiding tube, thus increasing tone quality.Type: GrantFiled: December 2, 2014Date of Patent: June 28, 2016Assignee: M2 Technology, Inc.Inventor: Chun-Yao Yang
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Publication number: 20160157009Abstract: An earphone with a speaker ring contains: a sound guiding tube, a speaker, and a body. The sound guiding tube is connected with the body, and the speaker is disposed in the sound guiding tube. The speaker has a first O ring fitted on a front end thereof and a second O ring fitted on a rear end thereof, and the first O ring and the second O ring are defined between the speaker and the sound guiding tube. Thereby, the first O ring, the second O ring, and the third O ring are arranged between the speaker and the sound guiding tube to reduce the resistance between the speaker and the sound guiding tube, thus increasing tone quality.Type: ApplicationFiled: December 2, 2014Publication date: June 2, 2016Inventor: Chun-Yao Yang
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Publication number: 20160157004Abstract: An earphone with at least one air orifice contains: a body. The body includes at least one slot defined on a rear cap thereof, and each of the at least one slot has at least one air orifice formed therein. Thereby, the air discharges or draws to vibrate the speaker via the at least one air orifice to reduce resistance of the air against the speaker and to enhance tone quality, when the speaker vibrates in a closed space.Type: ApplicationFiled: December 2, 2014Publication date: June 2, 2016Inventor: Chun-Yao Yang
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Publication number: 20150104914Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. The polysilicon layer is cryo-implanted with at least two of multiple species including a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between ?40° C. and ?120° C. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.Type: ApplicationFiled: November 24, 2014Publication date: April 16, 2015Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li
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Patent number: 8765588Abstract: A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess.Type: GrantFiled: September 28, 2011Date of Patent: July 1, 2014Assignee: United Microelectronics Corp.Inventors: Pong-Wey Huang, Chan-Lon Yang, Chang-Hung Kung, Wei-Hsin Liu, Ya-Hsueh Hsieh, Bor-Shyang Liao, Teng-Chun Hsuan, Chun-Yao Yang
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Publication number: 20130337622Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.Type: ApplicationFiled: August 20, 2013Publication date: December 19, 2013Applicant: United Microelectronics Corp.Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li