Abstract: A zero bias power detector comprising a zero bias diode and an output boost circuit is provided. The output boost circuit comprises a zero bias transistor. The zero bias diode is not biased but outputs a rectifying signal according to a wireless signal. The zero bias transistor, not biased but coupled to the zero bias diode, is used for enhancing the rectifying signal.

Abstract: A calibration device, capable of calibrating a gain of a radiometer, includes an actuator and a micro-electromechanical-system (MEMS) unit. The actuator receives a calibration signal outputted from a control unit. The MEMS unit is coupled to the actuator, in which the actuator enables the MEMS unit to shield an antenna of the radiometer according to the calibration signal, such that the radiometer generates an environmental signal according to an equivalent radiant temperature received from the MEMS unit, and the control unit calibrates the gain of the radiometer according to the environmental signal.

Abstract: An imaging system is provided, including a detection unit and a scan unit. The detection unit senses radiation of a target area. The scan unit directs the radiation to the detection unit, in which the scanning unit scans the target area N times at a constant speed within a scan period, such that each of the pixels of the target area is scanned N times by the scan unit, thereby the detection unit generates N sub-detection values for each of the pixels and adds the N sub-detection values up to generate a detection value for each of the pixels.

Abstract: The present invention discloses a power supply control circuit, the power supply providing an output voltage to an output terminal from an input terminal through a transformer having a primary winding and a secondary winding, the power supply control circuit comprising: a power switch electrically connected with the primary winding; a switch control circuit controlling the power switch; and a sensing circuit supplying an output signal to the switch control circuit according to voltage signals obtained from two sides of the primary winding, wherein the sensing circuit includes a setting circuit for deciding the output voltage according to a reference signal. The present invention also relates to a voltage sensing method in the power supply control circuit.

Abstract: The present invention discloses a power supply control circuit, the power supply providing an output voltage to an output terminal from an input terminal through a transformer having a primary winding and a secondary winding, the power supply control circuit comprising: a power switch electrically connected with the primary winding; a switch control circuit controlling the power switch; and a sensing circuit supplying an output signal to the switch control circuit according to voltage signals obtained from two sides of the primary winding, wherein the sensing circuit includes a setting circuit for deciding the output voltage according to a reference signal. The present invention also relates to a voltage sensing method in the power supply control circuit.

Abstract: An overlay mark set includes a substrate, a first overlay mark and a second overlay mark. The first overlay mark is disposed on the substrate for representing a first layout pattern. The second overlay mark is also disposed on the substrate for representing a second layout pattern. In particular, the first overlay mark is in direct contact with the second overlay mark.

Abstract: A method for fabricating a metal redistribution layer is described. A first opening and a second opening are formed in a dielectric layer over a first region and a second region thereof, respectively. A plurality of third openings are formed in the dielectric layer exposed by the first opening in the first region and a plurality of fourth openings are formed in the dielectric layer exposed by the second opening in the second region. A metal material is formed over the dielectric layer and in the first, second, third and fourth openings. A plurality of recesses is formed in the metal materials overlying the third and fourth openings. The metal material in the first region is patterned by using the recesses formed in portions of the metal material overlying the fourth openings in the second region as an alignment mark to form a metal redistribution layer.

Abstract: An alignment mark arrangement includes: a first alignment pattern comprising a plurality of parallel first stripes on a substrate, wherein each of the first stripes includes a first dimension; and a second alignment pattern positioned directly above and overlapping with the first alignment pattern, the second alignment pattern including a plurality of parallel second stripes, wherein each of the second stripes of the second alignment pattern has a second dimension that is larger than the first dimension of each of the first stripes of the first alignment pattern.

Abstract: A semiconductor manufacturing process is provided. First, a wafer with a material layer and an exposed photoresist layer formed thereon is provided, wherein the wafer has a center area and an edge area. Thereafter, the property of the exposed photoresist layer is varied, so as to make a critical dimension of the exposed photoresist layer in the center area different from that of the same in the edge area. After the edge property of the exposed photoresist layer is varied, an etching process is performed to the wafer by using the exposed photoresist layer as a mask, so as to make a patterned material layer having a uniform critical dimension formed on the wafer.

Abstract: A zero bias power detector comprising a zero bias diode and an output boost circuit is provided. The output boost circuit comprises a zero bias transistor. The zero bias diode is not biased but outputs a rectifying signal according to a wireless signal. The zero bias transistor, not biased but coupled to the zero bias diode, is used for enhancing the rectifying signal.

Abstract: A semiconductor lithography process. A photoresist film is coated on a substrate. The photoresist film is subjected to a flood exposure to blanket expose the photoresist film across the substrate to a first radiation with a relatively lower dosage. The photoresist film is then subjected to a main exposure using a photomask to expose the photoresist film in a step and scan manner to a second radiation with a relatively higher dosage. After baking, the photoresist film is developed.

Abstract: A semiconductor lithography process. A photoresist film is coated on a substrate. The photoresist film is subjected to a flood exposure to blanket expose the photoresist film across the substrate to a first radiation with a relatively lower dosage. The photoresist film is then subjected to a main exposure using a photomask to expose the photoresist film in a step and scan manner to a second radiation with a relatively higher dosage. After baking, the photoresist film is developed.

Abstract: A method for haze control in a semiconductor process, includes: providing an exposure tool with a photocatalyzer coating inside and exposing a wafer in the exposure tool in the presence of activation of the photocatalyzer coating. The photocatalyzer coating may be formed within an opaque region of a reticle.

Abstract: A semiconductor manufacturing process is provided. First, a wafer with a material layer and an exposed photoresist layer formed thereon is provided, wherein the wafer has a center area and an edge area. Thereafter, the property of the exposed photoresist layer is varied, so as to make a critical dimension of the exposed photoresist layer in the center area different from that of the same in the edge area. After the edge property of the exposed photoresist layer is varied, an etching process is performed to the wafer by using the exposed photoresist layer as a mask, so as to make a patterned material layer having a uniform critical dimension formed on the wafer.

Abstract: An alignment mark arrangement includes: a first alignment pattern comprising a plurality of parallel first stripes on a substrate, wherein each of the first stripes includes a first dimension; and a second alignment pattern positioned directly above and overlapping with the first alignment pattern, the second alignment pattern including a plurality of parallel second stripes, wherein each of the second stripes of the second alignment pattern has a second dimension that is larger than the first dimension of each of the first stripes of the first alignment pattern.

Abstract: A semiconductor manufacturing process is provided. First, a wafer with a material layer and an exposed photoresist layer formed thereon is provided, wherein the wafer has a center area and an edge area. Thereafter, the property of the exposed photoresist layer is varied, so as to make a critical dimension of the exposed photoresist layer in the center area different from that of the same in the edge area. After the edge property of the exposed photoresist layer is varied, an etching process is performed to the wafer by using the exposed photoresist layer as a mask, so as to make a patterned material layer having a uniform critical dimension formed on the wafer.

Abstract: The present invention discloses a power supply control circuit, the power supply providing an output voltage to an output terminal from an input terminal through a transformer having a primary winding and a secondary winding, the power supply control circuit comprising: a power switch electrically connected with the primary winding; a switch control circuit controlling the power switch; and a sensing circuit supplying an output signal to the switch control circuit according to voltage signals obtained from two sides of the primary winding, wherein the sensing circuit includes a setting circuit for deciding the output voltage according to a reference signal. The present invention also relates to a voltage sensing method in the power supply control circuit.

Abstract: A scanning exposure method is provided. A mask and a substrate are oppositely moved along a direction. The mask and the substrate are moved in at least two different uniform relative velocities during a one shot exposure, thus producing an exposed shot area of an expected size on the substrate.

Abstract: In a capacitor charger including a transformer having a primary winding connected with an input voltage and a secondary winding for transforming a primary current flowing through the primary winding to a secondary current flowing through the secondary winding, the primary current is adjusted according to a monitoring voltage varying with the input voltage, thereby prolonging the lifetime of the battery that provides the input voltage and improving the power efficiency of the battery.

Abstract: In a capacitor charger including a transformer having a primary winding connected with an input voltage and a secondary winding for transforming a primary current flowing through the primary winding to a secondary current flowing through the secondary winding, the primary current is adjusted according to a monitoring voltage varying with the input voltage, thereby prolonging the lifetime of the battery that provides the input voltage and improving the power efficiency of the battery.