Patents by Inventor Chun-Yen Huang

Chun-Yen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090195221
    Abstract: In a capacitor charger including a transformer having a primary winding connected with an input voltage and a secondary winding for transforming a primary current flowing through the primary winding to a secondary current flowing through the secondary winding, the primary current is adjusted according to a monitoring voltage varying with the input voltage, thereby prolonging the lifetime of the battery that provides the input voltage and improving the power efficiency of the battery.
    Type: Application
    Filed: March 30, 2009
    Publication date: August 6, 2009
    Inventors: Chung-Lung Pai, Kwan-Jen Chu, Chun-Yen Huang, Jing-Meng Liu
  • Patent number: 7248084
    Abstract: A method, which is for determining switching state of a transistor-based switching device that includes a set of transistors, includes the steps of: applying a bias voltage to a transistor having a fastest response so as to dispose the transistors in the set in a desired transistor state; detecting a voltage level at a transistor having a slowest response to the bias voltage; and comparing the detected voltage level with a predetermined threshold voltage level in order to determine the switching state of the switching device. A transistor-based switching device is also disclosed.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: July 24, 2007
    Assignee: Richtek Technology Corp.
    Inventors: Chun-Yen Huang, Hung-Der Su, Jing-Meng Liu, Chung-Lung Pai, Shih-Hui Chen, Yang-Ping Hung
  • Patent number: 7170763
    Abstract: In a capacitor charger, a transformer has a primary winding connected between an input voltage and a switch for generating a primary current flowing through the primary winding by switching the switch to thereby induce a secondary current flowing through a secondary winding of the transformer and a secondary voltage tapered from the secondary winding, a control apparatus and method adjusts the on-time period for the switch in response to the input voltage. The charging time and charging current are independent of the input voltage, and there is no power loss resulted from current sense to the primary current.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: January 30, 2007
    Assignee: Richtek Technology Corp.
    Inventors: Chung-Lung Pai, Kwan-Jen Chu, Chun-Yen Huang, Jing-Meng Liu
  • Patent number: 7132717
    Abstract: A power metal oxide semiconductor transistor layout is disclosed. The power metal oxide semiconductor transistor layout uses network of conductive lead line as a connection or a network connection to connect source and drain regions thereby achieves advantages of a high uniformity of current, low Rds_on, much less power loss, an actual line density two times larger than that of conventional layouts and a strengthened resistance to electron migration.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: November 7, 2006
    Assignee: Richtek Technology Corp.
    Inventors: Hung-Der Su, Chun-Yen Huang, Chung-Lung Pai, Jing-Meng Liu
  • Publication number: 20060138565
    Abstract: A power metal oxide semiconductor transistor layout is disclosed. The power metal oxide semiconductor transistor layout uses network of conductive lead line as a connection or a network connection to connect source and drain regions thereby achieves advantages of a high uniformity of current, low Rds_on, much less power loss, an actual line density two times larger than that of conventional layouts and a strengthened resistance to electron migration.
    Type: Application
    Filed: April 20, 2005
    Publication date: June 29, 2006
    Inventors: Hung-Der Su, Chun-Yen Huang, Chung-Lung Pai, Jing-Meng Liu
  • Publication number: 20060109046
    Abstract: A method, which is for determining switching state of a transistor-based switching device that includes a set of transistors, includes the steps of: applying a bias voltage to a transistor having a fastest response so as to dispose the transistors in the set in a desired transistor state; detecting a voltage level at a transistor having a slowest response to the bias voltage; and comparing the detected voltage level with a predetermined threshold voltage level in order to determine the switching state of the switching device. A transistor-based switching device is also disclosed.
    Type: Application
    Filed: April 19, 2005
    Publication date: May 25, 2006
    Inventors: Chun-Yen Huang, Hung-Der Su, Jing-Meng Liu, Chung-Lung Pai, Shih-Hui Chen, Yang-Ping Hung
  • Publication number: 20050140340
    Abstract: In a capacitor charger including a transformer having a primary winding connected with an input voltage and a secondary winding for transforming a primary current flowing through the primary winding to a secondary current flowing through the secondary winding, the primary current is adjusted according to a monitoring voltage varying with the input voltage, thereby prolonging the lifetime of the battery that provides the input voltage and improving the power efficiency of the battery.
    Type: Application
    Filed: December 22, 2004
    Publication date: June 30, 2005
    Inventors: Chung-Lung Pai, Kwan-Jen Chu, Chun-Yen Huang, Jing-Meng Liu
  • Publication number: 20050134235
    Abstract: In a capacitor charger, a transformer has a primary winding connected between an input voltage and a switch for generating a primary current flowing through the primary winding by switching the switch to thereby induce a secondary current flowing through a secondary winding of the transformer and a secondary voltage tapered from the secondary winding, a control apparatus and method adjusts the on-time period for the switch in response to the input voltage. The charging time and charging current are independent of the input voltage, and there is no power loss resulted from current sense to the primary current.
    Type: Application
    Filed: December 14, 2004
    Publication date: June 23, 2005
    Inventors: Chung-Lung Pai, Kwan-Jen Chu, Chun-Yen Huang, Jing-Meng Liu
  • Patent number: 6577020
    Abstract: High contrast alignment marks that can be flexibly located on a semiconductor wafer are disclosed. The wafer has a first layer and a second layer. The first layer has a light-dark intensity and a reflectivity. The second layer is over the first layer, and has a light-dark intensity substantially lighter than that of the first layer, and a higher reflectivity than that of the first layer. The first layer may be patterned to further darken it. The second layer contrasts visibly to the first layer, and is patterned to form at least one or more alignment marks within the second layer. The first layer may be a metallization layer, such as titanium nitride, whereas the second layer may be a metallization layer, such as aluminum or copper.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: June 10, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chun-Yen Huang, Chien-Ye Lee, Ju-Bin Fu, Rong-I Peng
  • Publication number: 20030071369
    Abstract: High contrast alignment marks that can be flexibly located on a semiconductor wafer are disclosed. The wafer has a first layer and a second layer. The first layer has a light-dark intensity and a reflectivity. The second layer is over the first layer, and has a light-dark intensity substantially lighter than that of the first layer, and a higher reflectivity than that of the first layer. The first layer may be patterned to further darken it. The second layer contrasts visibly to the first layer, and is patterned to form at least one or more alignment marks within the second layer. The first layer may be a metallization layer, such as titanium nitride, whereas the second layer may be a metallization layer, such as aluminum or copper.
    Type: Application
    Filed: October 11, 2001
    Publication date: April 17, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Yen Huang, Chien-Ye Lee, Ju-Bin Fu, Rong-I Peng
  • Patent number: 5520281
    Abstract: A product card of hooks comprising a sheet of paper card base having both sides covered with a respective strippable cover film, the sheet of paper card base being punched into a plurality of disposable hooks in it, the disposable hooks having tiny connecting portions maintained linked to the sheet of paper card base, each disposable hook comprising an elongated body having two opposite ends turned inwards and formed into an open hook portion and a close hook portion respectively.
    Type: Grant
    Filed: May 8, 1995
    Date of Patent: May 28, 1996
    Inventor: Chun-Yen Huang