Abstract: A fabricating method of a non-woven film, for electronic components, includes the following steps. Providing a polyetherimide substrate and an aerogel dispersion, in which the aerogel dispersion includes an aerogel, and the aerogel has a moisture content between 0.7% and 0.9% and a porosity between 85% and 95%. Dipping the polyetherimine substrate in the aerogel dispersion, such that the aerogel dispersion covers the polyetherimine substrate. Performing a thermal compression process on the polyetherimide substrate, such that the aerogel and the polyetherimide substrate are composited with each other. Performing an ultrasonic oscillating process on the polyetherimine substrate, such that the aerogel not being composited with the polyetherimine substrate is removed.

Abstract: A liquid cooling module is used to cool a lighting module. The liquid cooling module includes a first cooling unit, a second cooling unit, a heat dissipation component and a pipeline component. The first cooling unit includes a first communication surface and a first cooling surface. The second cooling unit includes a top surface, a second communication surface and a second cooling surface. The top surface is perpendicular to the first communication surface and opposite to the second cooling surface. The pipeline component includes a first pipeline, a second pipeline and a third pipeline. The first pipeline is connected to the heat dissipation component and the first communication surface, the second pipeline is connected to the first communication surface and the second communication surface, and the third pipeline is connected to the second communication surface and the heat dissipation component. In addition, a projection device is also mentioned.

Abstract: A wideband antenna system includes a first metal radiation portion, having a coupling distance with a second metal radiation portion; a first feeding contact and a second feeding contact, electrically connected to the first metal radiation portion and the second metal radiation portion respectively, and close to the coupling distance; a first ground contact, electrically connected to the second metal radiation portion; a second ground contact, electrically connected to the first metal radiation portion; an impedance tuner, electrically connected to the first feeding contact, the second feeding contact, the first ground contact, the second ground contact, and a radio frequency signal source, to switch the first metal radiation portion and the second metal radiation portion; an aperture contact, electrically connected to the first metal radiation portion; and an aperture tuner, electrically connected to the aperture contact.

Abstract: The present disclosure provides a device and method for inserting an IOL into an eye of a patient. The IOL injector can be configured to preload an IOL into the lens cartridge of the injector without manual manipulation of the IOL by the nurse and/or physician during the procedure. The injector can be configured to properly orient and align the IOL within the injector and maintain proper alignment throughout delivery of the IOL to the eye of a patient and thereby ensuring that the IOL is properly positioned and oriented at a predetermined location in the eye.

Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.

Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.

Abstract: An automatic vehicle-door activating sensing system and a method therefor are provided. The system includes: a distance sensing antenna module and an activating antenna module for generating signals; a processor generates a first distance information, a second distance information, and a activating information according to the signals. When the first distance information is less than a distance threshold and a waveform of the activating information changes, the processor generates and transmits a ready-to-activate signal to an in-vehicle system. When the second distance information is greater than the distance threshold, the processor generates and transmits a vehicle door activating signal to the in-vehicle system. The in-vehicle system can activate the vehicle door after receiving the signals in sequence. With one radar, the invention can automatically activate the vehicle door based on a user's position and kicking behavior, thereby preventing misoperation caused by detection.

Abstract: A method performed by a User Equipment (UE) for handling timing alignment is provided. The method receives, from a Base Station (BS), a first Radio Resource Control (RRC) message for configuring a Time Alignment Timer (TAT). The method receives, from the BS, a second RRC message for configuring at least one of a cell Discontinuous Transmission (DTX) operation or a cell Discontinuous Reception (DRX) operation. In a case that at least one of the cell DTX operation or the cell DRX operation is configured and the TAT expires, the method considers the UE to be uplink synchronized with the BS and forgoes performing a procedure for handling an out-of-sync condition related to the expiration of the TAT.

Abstract: A package structure includes a circuit substrate, a package unit, a thermal interface material and a cover. The package unit is disposed on and electrically connected with the circuit substrate. The package unit includes a first surface facing the circuit substrate and a second surface opposite to the first surface. A underfill is disposed between the package unit and the circuit substrate, surrounding the package unit and partially covering sidewalls of the package unit. The cover is disposed over the package unit and over the circuit substrate. An adhesive is disposed on the circuit substrate and between the cover and the circuit substrate. The thermal interface material includes a metal-type thermal interface material and is disposed between the cover and the package unit. The thermal interface material physically contacts the second surface and the sidewalls of the package unit and physically contacts the underfill.

Abstract: An integrated circuit is provided, including a first transistor of a first conductivity type comprising first and second active regions, a second transistor of a second conductivity type comprising third and fourth active regions and arranged under the first transistor along a first direction, a first gate structure extending in the first direction and shared by the first and second transistors, an isolation layer sandwiched between the first and second transistors and extending along a second direction to pass through the first gate structure, and a connection layer surrounded by the isolation layer and extending along the second direction to pass through the first gate structure. The isolation layer has a first surface contacting the first and second active regions and a second surface contacting the third and fourth active regions. The connection layer comprises first and second portions are electrically coupled to the first and fourth active regions.

Abstract: A non-woven film for electronic components is provided in the present disclosure. The non-woven film for electronic components includes a polyetherimide substrate and an aerogel. The aerogel is disposed on the polyetherimide substrate. The aerogel has a moisture content between 0.7% and 0.9% and a porosity between 85% and 95%.

Abstract: A method for evaluating appropriateness of dosage of a target drug administered to a patient is adapted to be implemented by a computing device that stores a dosage evaluation model. The method comprises steps of: obtaining at least one physiological parameter that is related to a physiological condition of the patient; obtaining at least one medication parameter that is related to a usage condition of the target drug by the patient; and feeding said at least one physiological parameter and said at least one medication parameter into the dosage evaluation model to obtain an evaluation result that indicates the appropriateness of the dosage of the target drug administered to the patient.

Abstract: An integrated circuit is provided which includes a first complementary field-effect transistor and a second complementary field-effect transistor. The first complementary field-effect transistor includes at least two first transistors respectively located on a first layer and a second layer. The second complementary field-effect transistor is disposed adjacent to the first complementary field-effect transistor. The second complementary field-effect transistor includes at least two second transistors respectively located on the first layer and the second layer. Type of one of the at least two first transistors located on the first layer is different from type of one of the at least two second transistors located on the first layer.

Abstract: A method includes: forming a first channel structure through a first gate structure; forming a first source/drain structure coupled to the first channel structure at a first surface of the first gate structure; before the first source/drain structure is formed, forming a first isolation layer at a second surface of the first gate structure to isolate the first channel structure; and after the first source/drain structure is formed, forming a first insulation structure at a position of the first isolation layer. The first surface and the second surface are opposite to each other, and a size of the first insulation structure is equal to or larger than a size of the first source/drain structure.

Abstract: An IC device in some embodiments includes a first conductive line in a first conductive layer disposed in a first plane, a second conductive line in a second conductive player disposed in a second plane, and a conductor connecting first and second conductive lines, the conductor including a conductive wall disposed in a plane substantially transverse to the first plane and have a length in a direction substantially parallel to the first plane and a height in a direction substantially transverse to the first plane. The conductive wall in some embodiments includes a conductive plate electrically interconnecting two metal diffusion regions each of which electrically connected to a respective one of the first and second conductive lines. The conductive wall in other embodiments includes two metal diffusion regions abutting each other, each of the metal diffusion regions electrically connected to a respective one of the first and second conductive lines.

Abstract: A capillary refill time determining system is configured to judge a color variation of an image, and the capillary refill time determining system includes an electronic device including an image capturing unit, a storage unit and a processor. The storage unit is configured to access a refill start time and a default value. The processor is electronically connected to the image capturing unit and the storage unit, and the processor is configured to analyze an average color value of the image at an initial period, wherein at least one refill color value is obtained by analyzing the image according to the refill start time, the difference between the average color value and the refill color value is confirmed whether less than or equal to the default value, and a refill period is calculated between the refill start time and the refill end time.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a fin of semiconductor material protruding outward from an upper surface of a substrate. A doped region is arranged within the fin of semiconductor material and laterally between a first region and a second region of the fin of semiconductor material. A first gate structure is over the first region of the fin of semiconductor material, a second gate structure is over the second region of the fin of semiconductor material, and a third gate structure is over the doped region. Source/drain regions are between the first gate structure, the second gate structure, and the third gate structure.

Abstract: A method includes receiving an integrated circuit (IC) design layout including a layout block, where the layout block including first line patterns disposed along a first direction, extending lengths of the first line patterns, connecting portions of the first line patterns disposed within a distance less than a preset value, forming second line patterns disposed outside the layout block parallel to the first line patterns, forming mandrel bar patterns overlapping edges of the layout block, where the mandrel bar patterns oriented along a second direction perpendicular to the first direction, and outputting a pattern layout for mask fabricating, where the pattern layout includes the layout block, the first and second line patterns, and the mandrel bar patterns.

Abstract: A device includes: an active region extending in a first direction; a first metal-to-S/D (MD) contact structure extending in a perpendicular second direction, and over and coupled to the active region; a first layer of metallization over the first MD contact structure and having M_1st segments extending in the first direction and each having a substantially same width relative to the second direction, the M_1st segments including M_1st routing segments, and an M_1st power grid (PG) segment having a portion over and coupled to the first MD contact structure; a second layer of metallization over the first layer of metallization and having M_2nd segments that extend in the second direction and include an M_2nd PG rail configured for a first reference voltage, a portion thereof being over and coupled to the M_1st PG segment. the M_2nd PG rail extending across multiple cell regions.

Abstract: A device includes a first transistor layer comprising a first gate electrode and a second transistor layer comprising a second gate electrode that is stacked with the first transistor layer. n intermetal structure comprising a conductive line is disposed between the first transistor layer and the second transistor layer. A first gate contact extends along a sidewall of the first gate electrode from a top surface of the first gate electrode to the conductive line 48G. A second gate contact extends along a sidewall of the second gate electrode from a top surface of the second gate electrode to the conductive line. The first gate electrode is electrically connected to the second gate electrode by the first gate contact, the second gate contact, and the conductive line.