Abstract: A memory is provided with a pseudo-differential sense amplifier for single-endedly sensing a first read bit line from a first bank of bitcells. The sense amplifier compares a voltage of the first read bit line to a voltage of a pre-charged second read bit line from a second bank of bitcells to make a bit decision for a read operation through the first read bit line to the first bank of bitcells.

Abstract: A semiconductor device including a first active area layer that extends in a first direction, a first metal over diffusion layer that extends in a second direction that is different than the first direction, the first metal over diffusion layer situated over the first active area layer, a first gate that extends in the second direction and over the first active area layer, a first gate end of the first gate that abuts a first dielectric region, and first low-k dielectric material situated in the first dielectric region.

Abstract: A device includes: a first cell region stacked on a second cell region; each including a first active region over a second active region; in a first layer of metallization (M_first layer) over the first active region, M_first power grid (PG) segments having a first reference voltage and M_first routing segments aligned correspondingly to M_first routing tracks; and in a first layer of metallization (BM_first layer) under the second active region, BM_first PG segments having a second reference, and BM_first routing segments aligned correspondingly to BM_first routing tracks. The M_first routing segments are aligned in the first and second cell regions correspondingly to first (Q1) and second (Q2) quantities of the M_first routing tracks, where Q2<Q1. The BM_first routing segments are aligned in the first and second cell regions correspondingly to third and fourth quantities of the BM_first routing tracks, where Q4<Q3.

Abstract: A method includes forming a first complementary Field-Effect Transistor (CFET) and a second CFET. The first CFET includes a first lower transistor, and a first upper transistor overlapping the first lower transistor. The second CFET includes a second lower transistor, and a second upper transistor overlapping the second lower transistor. The method further includes performing a first etching process to form a first opening, wherein the first etching process includes etching a first gate stack between the first upper transistor and the second upper transistor, and etching a second gate stack between the first lower transistor and the second lower transistor. The first opening is filled with a dielectric material to form a dielectric region. The method further includes performing a second etching process to etch a middle portion of the dielectric region and to form a second opening, and filling the second opening with a conductive material to form a through-via.

Abstract: An integrated circuit is provided, including a first transistor of a first conductivity type comprising first and second active regions, a second transistor of a second conductivity type comprising third and fourth active regions and arranged under the first transistor along a first direction, a first gate structure extending in the first direction and shared by the first and second transistors, an isolation layer sandwiched between the first and second transistors and extending along a second direction to pass through the first gate structure, and a connection layer surrounded by the isolation layer and extending along the second direction to pass through the first gate structure. The isolation layer has a first surface contacting the first and second active regions and a second surface contacting the third and fourth active regions. The connection layer comprises first and second portions are electrically coupled to the first and fourth active regions.

Abstract: An integrated circuit is provided which includes a first complementary field-effect transistor and a second complementary field-effect transistor. The first complementary field-effect transistor includes at least two first transistors respectively located on a first layer and a second layer. The second complementary field-effect transistor is disposed adjacent to the first complementary field-effect transistor. The second complementary field-effect transistor includes at least two second transistors respectively located on the first layer and the second layer. Type of one of the at least two first transistors located on the first layer is different from type of one of the at least two second transistors located on the first layer.

Abstract: A method includes: forming a first channel structure through a first gate structure; forming a first source/drain structure coupled to the first channel structure at a first surface of the first gate structure; before the first source/drain structure is formed, forming a first isolation layer at a second surface of the first gate structure to isolate the first channel structure; and after the first source/drain structure is formed, forming a first insulation structure at a position of the first isolation layer. The first surface and the second surface are opposite to each other, and a size of the first insulation structure is equal to or larger than a size of the first source/drain structure.

Abstract: An IC device in some embodiments includes a first conductive line in a first conductive layer disposed in a first plane, a second conductive line in a second conductive player disposed in a second plane, and a conductor connecting first and second conductive lines, the conductor including a conductive wall disposed in a plane substantially transverse to the first plane and have a length in a direction substantially parallel to the first plane and a height in a direction substantially transverse to the first plane. The conductive wall in some embodiments includes a conductive plate electrically interconnecting two metal diffusion regions each of which electrically connected to a respective one of the first and second conductive lines. The conductive wall in other embodiments includes two metal diffusion regions abutting each other, each of the metal diffusion regions electrically connected to a respective one of the first and second conductive lines.

Abstract: A capillary refill time determining system is configured to judge a color variation of an image, and the capillary refill time determining system includes an electronic device including an image capturing unit, a storage unit and a processor. The storage unit is configured to access a refill start time and a default value. The processor is electronically connected to the image capturing unit and the storage unit, and the processor is configured to analyze an average color value of the image at an initial period, wherein at least one refill color value is obtained by analyzing the image according to the refill start time, the difference between the average color value and the refill color value is confirmed whether less than or equal to the default value, and a refill period is calculated between the refill start time and the refill end time.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a fin of semiconductor material protruding outward from an upper surface of a substrate. A doped region is arranged within the fin of semiconductor material and laterally between a first region and a second region of the fin of semiconductor material. A first gate structure is over the first region of the fin of semiconductor material, a second gate structure is over the second region of the fin of semiconductor material, and a third gate structure is over the doped region. Source/drain regions are between the first gate structure, the second gate structure, and the third gate structure.

Abstract: A method includes receiving an integrated circuit (IC) design layout including a layout block, where the layout block including first line patterns disposed along a first direction, extending lengths of the first line patterns, connecting portions of the first line patterns disposed within a distance less than a preset value, forming second line patterns disposed outside the layout block parallel to the first line patterns, forming mandrel bar patterns overlapping edges of the layout block, where the mandrel bar patterns oriented along a second direction perpendicular to the first direction, and outputting a pattern layout for mask fabricating, where the pattern layout includes the layout block, the first and second line patterns, and the mandrel bar patterns.

Abstract: A device includes: an active region extending in a first direction; a first metal-to-S/D (MD) contact structure extending in a perpendicular second direction, and over and coupled to the active region; a first layer of metallization over the first MD contact structure and having M_1st segments extending in the first direction and each having a substantially same width relative to the second direction, the M_1st segments including M_1st routing segments, and an M_1st power grid (PG) segment having a portion over and coupled to the first MD contact structure; a second layer of metallization over the first layer of metallization and having M_2nd segments that extend in the second direction and include an M_2nd PG rail configured for a first reference voltage, a portion thereof being over and coupled to the M_1st PG segment. the M_2nd PG rail extending across multiple cell regions.

Abstract: A device includes a first transistor layer comprising a first gate electrode and a second transistor layer comprising a second gate electrode that is stacked with the first transistor layer. n intermetal structure comprising a conductive line is disposed between the first transistor layer and the second transistor layer. A first gate contact extends along a sidewall of the first gate electrode from a top surface of the first gate electrode to the conductive line 48G. A second gate contact extends along a sidewall of the second gate electrode from a top surface of the second gate electrode to the conductive line. The first gate electrode is electrically connected to the second gate electrode by the first gate contact, the second gate contact, and the conductive line.

Abstract: A respiratory system includes a gas supply unit and a heating and humidifying unit. The gas supply unit includes a gas supply port; the heating and humidifying unit is detachably combined with the gas supply unit. The heating and humidifying unit includes a base, an adapter and a water tank. The base includes a control element, and the adapter is combined with the base and can rotate at least 90 degrees relative to the base. The water tank is detachably combined with the base, and the water tank includes a gas inlet and a gas outlet, wherein when the water tank is combined with the base, the gas inlet penetrates through an aperture of the base to be fluidly connected to the gas supply port, and the gas outlet is fluidly connected to the adapter.

Abstract: An integrated circuit (IC) device includes a complementary field-effect transistor (CFET) device, a power rail at a first side of the CFET device, and a conductor at a second side of the CFET device. The CFET device includes a local interconnect. The first side is one of a front side and a back side of the CFET device. The second side is the other of the front side and the back side of the CFET device. The local interconnect of the CFET device electrically couples the power rail to the conductor.

Abstract: In some embodiments, the present disclosure relates to a method that includes removing portions of a substrate to form a continuous fin protruding from an upper surface of the substrate. A doping process is performed to selectively increase a dopant concentration of a first portion of the continuous fin. A first gate electrode is formed over a second portion of the continuous fin, and a second gate electrode is formed over a third portion of the continuous fin. The first portion of the continuous fin is between the second and third portions of the continuous fin. A dummy gate electrode is formed over the first portion of the continuous fin. Upper portions of the continuous fin that are arranged between the first gate electrode, the second gate electrode, and the dummy gate electrode are removed, and source/drain regions are formed between the first, the second, and the dummy gate electrodes.

Abstract: A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.

Abstract: An integrated circuit (IC) device includes a bottom semiconductor device, a top semiconductor device over the bottom semiconductor device in a thickness direction of the IC device, and a multilayer structure between the bottom semiconductor device and the top semiconductor device in the thickness direction. The multilayer structure includes a lower dielectric layer over the bottom semiconductor device, an upper dielectric layer over the lower dielectric layer, and an interlayer metal structure between the lower dielectric layer and the upper dielectric layer. The interlayer metal structure is electrically coupled to at least one of the bottom semiconductor device or the top semiconductor device.

Abstract: A memory is provided with a pseudo-differential sense amplifier for single-endedly sensing a first read bit line from a first bank of bitcells. The sense amplifier compares a voltage of the first read bit line to a voltage of a pre-charged second read bit line from a second bank of bitcells to make a bit decision for a read operation through the first read bit line to the first bank of bitcells.

Abstract: An integrated circuit is provided, including a first cell. The first cell includes a first pair of active regions, at least one first gate, two first conductive segments, and a first interconnect structure. The first pair of active regions extends in a first direction and stacked on each other. The at least one first gate extends in a second direction different from the first direction, and is arranged across the first pair of active regions, to form at least one first pair of devices that are stacked on each other. The first conductive segments are coupled to the first pair of active regions respectively. The first interconnect structure is coupled to at least one of a first via or one of the two first conductive segments.