Abstract: A method of manufacturing a memory device includes providing a substrate and sequentially forming a stack layer and a hard mask layer on the substrate. The method includes forming a first patterned mandrel and a plurality of second patterned mandrels on the hard mask layer, wherein the first patterned mandrel is adjacent to and spaced apart from an end of the second patterned mandrels in the first direction. The method further includes using the first patterned mandrel and the second patterned mandrels as masks, patterning the hard mask layer and the stack layer sequentially to form a dummy structure and a plurality of word lines separated from each other on the substrate. A portion of the stack layer corresponding to the first mandrel is formed into the dummy structure, and a portion of the stack layer corresponding to the second patterned mandrels is formed into the word lines.

Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.

Abstract: Provided is an anesthetic composition for locally administering a local anesthetic agent to a subject in need thereof. The anesthetic composition has a lipid based complex prepared by hydrating a lipid cake containing a local anesthetic agent and a lipid mixture with an aqueous buffer solution at a pH higher than 5.5. Also provided is a method to prepare an anesthetic composition using a simpler and more robust for large-scale manufacture and for providing a high molar ratio of local anesthetic agent to phospholipid content as compared to the prior art. This anesthetic composition has a prolonged duration of efficacy adapted to drug delivery.

Abstract: The present application relates to a system and a method for producing vinyl chloride. The system comprise a preheat unit, a gas-liquid separating unit, a heat-recovery unit, a heating unit and a thermal pyrolysis unit, and therefore heat energy of the thermal pyrolysis product can be efficiently recovered. Energy cost of the system can be efficiently lowered with the heat-recovery unit and the heating unit, and further prolonging operating cycle of the system.

Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.

Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

Abstract: A semiconductor device (having a CMOS architecture) includes first to fourth cell regions Each of the first and second cell regions includes a pair of first and second stacks of nanosheets relative to, e.g., the Z-axis. The nanosheets of the first stack have a first dopant-type, e.g., N-type. The nanosheets of the second stack have a second dopant type, e.g., P-type. Each pair of first and second stacks represents a CMOS architecture relative to a second direction, e.g., the Y-axis Each of the third and fourth cell regions has CFET architecture, the CFET architecture being a type of CMOS architecture relative to the Z-axis. The third and fourth cell regions are adjacent each other relative to the Y-axis. The first and second active regions are on corresponding first and second sides of each of the third and fourth active regions. The first and second cell regions are non-CFET cell regions.

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes: at least one gate structure having a first side and a second side opposite to each other; a first source/drain (S/D) feature disposed at the first side of the at least one gate structure; a second S/D feature disposed at the second side of the at least one gate structure; a first metal-to-drain/source (MD) contact disposed on the first S/D feature; and a second MD contact disposed on the second S/D feature, wherein a contact area between the first MD contact and the first S/D feature is greater than a contact area between the second MD contact and the second S/D feature.

Abstract: An integrated circuit (IC) structure includes a fin structure protruding from a semiconductor substrate, the fin structure including a first portion having a first width, a second portion having a second width that is different from the first width, and a third portion extending continuously along a first direction over the semiconductor substrate, the first width and the second width being measured along a second direction perpendicular to the first direction. The IC structure also includes a first standard cell including a first metal gate stack engaged with the first portion, a second standard cell including a second metal gate stack engaged with the second portion, and a filler cell disposed between the first standard cell and the second standard cell, where the filler cell includes the third portion that connects the first portion to the second portion.

Abstract: A semiconductor device includes a first transistor, a second transistor, a third transistor, and a contact. The first transistor includes a first source/drain (S/D), a second S/D, and a first gate between the first S/D and the second S/D. The first transistor and the second transistor are stacked over the third transistor. The contact covers the second S/D of the first transistor. The contact is electrically connected to the second transistor and electrically isolated from the second S/D.

Abstract: A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.

Abstract: A method for forming a pattern layout is provided, including receiving an IC design layout including a layout block, a first line pattern is disposed inside the layout block along the first direction; forming a second line pattern disposed outside the layout block parallel to the first line patterns; forming a mandrel bar pattern oriented along the second direction and overlapping the first line pattern and the second line pattern, the mandrel bar pattern is between the first edge and the third edge of the layout block that are parallel to the first direction, and a first end of the mandrel bar pattern is separated from the first edge and overlaps a first side edge of one of the first line pattern or the second line pattern closest to the first edge; and outputting a pattern layout.

Abstract: In some embodiments, the present disclosure relates to a method that includes removing portions of a substrate to form a continuous fin protruding from an upper surface of the substrate. A doping process is performed to selectively increase a dopant concentration of a first portion of the continuous fin. A first gate electrode is formed over a second portion of the continuous fin, and a second gate electrode is formed over a third portion of the continuous fin. The first portion of the continuous fin is between the second and third portions of the continuous fin. A dummy gate electrode is formed over the first portion of the continuous fin. Upper portions of the continuous fin that are arranged between the first gate electrode, the second gate electrode, and the dummy gate electrode are removed, and source/drain regions are formed between the first, the second, and the dummy gate electrodes.

Abstract: In some embodiments, the present disclosure relates to a method that includes removing portions of a substrate to form a continuous fin over the substrate. Further, a doping process is performed to selectively increase a dopant concentration of a first portion of the continuous fin. A first gate electrode is formed over a second portion of the continuous fin, and a second gate electrode is formed over a third portion of the continuous fin. The first portion of the continuous fin is between the second portion and the third portion of the continuous fin. A dummy gate electrode is formed over the first portion of the continuous fin. Upper portions of the continuous fin that are arranged between the first gate electrode, the second gate electrode, and the dummy gate electrode are removed, and source/drain regions are formed between the first, the second, and the dummy gate electrodes.

Abstract: A method for forming sense amplifiers of a memory device includes: determining a type of each bitline selector used to provide a data signal to a corresponding sense amplifier; forming a plurality of separate active areas in a substrate of the memory device along one of a column direction and a row direction according to the type of the bitline selector, the substrate including a plurality of cell columns, each of the cell columns having a plurality of memory cells arranged along the column direction, each of the active areas being formed across a boundary between two adjacent cell columns and located within the adjacent cell columns; and arranging a plurality of gate structures on the active areas to form transistors of the sense amplifiers, each gate structure extending in the row direction.

Abstract: A semiconductor device includes a first cell in a first row, wherein the first row extends in a first direction, the first cell having a first cell height measured in a second direction perpendicular to the first direction. The semiconductor device further includes a second cell in the first row, wherein the second cell has a second cell height measured in the second direction, the second cell height is less than the first cell height. The second cell includes a first active region having a first width measured in the second direction, and a second active region having a second width measured in the second direction, wherein the second width is different from the first width.

Abstract: A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.

Abstract: A semiconductor structure includes a substrate; a first column of active regions over the substrate; a second column of active regions over the substrate; and a dummy padding disposed between the first and the second columns from a top view. The dummy padding includes multiple dummy regions. A first dummy region of the multiple dummy regions is disposed between a first active region in the first column of active regions and a second active region in the second column of active regions. An outer boundary line tracing an edge of the first active region, an edge of the first dummy region, and an edge of the second active region includes at least two substantially 90-degree bends from a top view. The first and the second active regions include a semiconductor material doped with a same dopant.

Abstract: Multiphase trans-inductor voltage regulator fault diagnostic. One example is a method of detecting electrical faults in a multiphase power converter, the method comprising: driving, by a controller of the multiphase power converter, a first phase of the power converter, the first phase comprising a phase-one transformer module; driving, by the controller, a second phase of the power converter, the second phase comprising a phase-two transformer module distinct from the phase-one transformer module; testing, by the controller of the multiphase power converter, for a phase-one electrical fault associated with the phase-one transformer module; testing, by the controller, for a phase-two electrical fault associated with the phase-two transformer module; and driving, by the controller, a fault indicator in the presence of a phase-one or phase-two electrical fault.

Abstract: A fingerprint sensing device and a driving method for a fingerprint sensing panel thereof are provided. The driving method includes: detecting whether a finger touch occurs on the fingerprint sensing panel; during a period of the finger touch, switching the brightness mode of the fingerprint sensing panel from a normal brightness mode to a high brightness mode so as to sense a fingerprint; driving the fingerprint sensing panel to sense the fingerprint before a mode switching time point at which the brightness mode of the fingerprint sensing panel is switched to the high brightness mode. The fingerprint sensing panel includes a pixel row, wherein the pixel row is subjected to a reset, an exposure period and a sampling in sequence to output a row sensing result, the reset is earlier than the mode switching time point, and the sampling is later than the mode switching time point.