Abstract: An electronic component transfer apparatus is configured to transfer an electronic component on a flexible carrier to a target substrate. The electronic component transfer apparatus includes a first frame, a second frame, an abutting component, an actuating mechanism, an energy generating device, an image capture device, and a data processing module. The first frame is configured to carry the flexible carrier. The second frame is configured to carry the target substrate. The abutting component is disposed adjacent to the flexible carrier. The actuating mechanism is configured to actuate the abutting component, so that the abutting end of the abutting component abuts against the flexible carrier. The energy generating device generates an energy beam. The image capture device captures an image through the abutting component. The data processing module receives and computes the image to determine whether to adjust the relative position between the abutting end and the flexible carrier.

Abstract: A circuit assembly includes an IC die and a stack of capacitor dies. The IC die has a first hybrid bonding layer. The stack of capacitor dies includes a first capacitor die and a second capacitor die. The first capacitor die has a second hybrid bonding layer in contact with the first hybrid bonding layer. The second capacitor die is stacked over the first capacitor die. The first capacitor die has a third hybrid bonding layer. The second capacitor die has a fourth hybrid bonding layer coupled to the third hybrid bonding layer. The second capacitor die has a first side and a second side, the fourth hybrid bonding layer is formed on the second side, a plurality of conductive vias is formed on the first side, and the second capacitor die further comprises a plurality of interface bumps electrically connecting to the conductive vias.

Abstract: A circuit assembly includes an integrated circuit (IC) die and a capacitor die. The IC die has a first hybrid bonding layer. The capacitor die is stacked with the IC die, and is configured to include a capacitor coupled to the IC die, and has a second hybrid bonding layer in contact with the first hybrid bonding layer; wherein the IC die is electrically coupled to the capacitor die through the first hybrid bonding layer and the second hybrid bonding layer.

Abstract: A display controller includes a first chip and a second chip. The first chip is configured to control a display device. The second chip is externally coupled to the first chip, and configured to be a random access memory and. The first chip is further configured to provide a first supply power to the second chip and to access the second chip during the controlling of the display device.

Abstract: An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage. The at least one data terminal receives a first data signal that varies between a second high voltage and the low voltage during a command phase, and transmits or receives a second data signal during a data phase. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage during the command phase, and transmits or receives a second data strobe signal that swings periodically during the data phase. During a transition interval between the command phase and the data phase, the data strobe terminal stops receiving or transmitting data strobe signals that swing periodically.

Abstract: An acoustic wave element includes: a substrate; a bonding structure on the substrate; a support layer on the bonding structure; a first electrode including a lower surface on the support layer; a cavity positioned between the support layer and the first electrode and exposing a lower surface of the first electrode; a piezoelectric layer on the first electrode; and a second electrode on the piezoelectric layer, wherein at least one of the first electrode and the second electrode includes a first layer and a second layer that the first layer has a first acoustic impedance and a first electrical impedance, the second layer has a second acoustic impedance and a second electrical impedance, wherein the first acoustic impedance is higher than the second acoustic impedance, and the second electrical impedance is lower than the first electrical impedance.

Abstract: An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage for enabling the memory circuit. The at least one data terminal receives at least one first data signal that varies between a second high voltage and the low voltage. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage. The first data strobe signal is synchronized with the at least one first data signal, and is arranged to latch and sample the at least one first data signal. The first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage.

Abstract: A brain tumor types distinguish system includes an image outputting device and a server computing device. The image outputting device outputs at least three brain images captured from the position of a brain tumor. The server computing device pre-stores a plurality of distinguish pathways corresponding to different types of brain tumors. The server computing device includes an image receiving module, an image pre-processing module, a data comparison module and a distinguish module. The image receiving module receives the brain images. The image pre-processing module pre-processes the brain images to obtain corresponding processed images thereof. The data comparison module compares the brain images and the processed images with the distinguish pathways to obtain at least three comparison results. The distinguish module statistically analyzes the comparison results to obtain a distinguish result.

Abstract: A method of extracting parasitic parameters of a 3D IC is provided in the present invention, including steps of providing a 3D IC having multiple dies, merging respective layouts of the multiple dies into a common layout, creating a common LVS file and a common LPE file for those multiple dies based on the common layout, creating respective LVS files and respective LPE files for every die based on the respective layouts, creating a common netlist from the common LVS file and common LPE file, creating corresponding respective netlists from the respective LVS files and respective LPE files, merging the common netlist and respective netlists into a netlist, and extracting common parasitic parameters of the dies from the netlist.

Abstract: A method to manufacture a semiconductor device includes: bonding a first wafer and a second wafer to be stacked vertically with one another, in which the first wafer provides a plurality of memory components and the second wafer provides a control circuit; forming a plurality of input/output channels on a surface of one of the first and second wafers; and cutting the bonded first and second wafers into a plurality of dices; wherein a plurality of first conductive contacts in the first wafer are electrically connected to the control circuit and the first conductive contacts in combinations with a plurality of first conductive vias in the first wafer form a plurality of transmission channels through which the control circuit is capable to access the memory components.

Abstract: A heat dissipating mechanism is for heat dissipation of a display module and a heat generating module of a display apparatus and includes a frame structure, a first airflow generating device, and a conductive cover structure having first, second, and third covers. The first cover is connected to the frame structure for containing the display module. The second cover has an air inlet and an air outlet and is connected to the first cover to form a channel. The third cover is connected to the second cover for containing the heat generating module. The first airflow generating device is disposed in the air inlet to guide air into the channel and out of the air outlet, so as to form an airflow for heat dissipation of the display module and the heat generating module.

Abstract: A target image of a target circuit board and a gold image of a gold circuit board are taken by an image acquisition system. Fiducial points are located on the target image and on the gold image. Perspective transformation is performed on the target image using the fiducial points on the target image for reference and on the gold image using the fiducial points on the gold image for reference. After perspective transformation, an anomalous section of the target image is identified by identifying pixels that have different intensities between the target image and the gold image, the anomalous section being indicative of an unauthorized modification to the target circuit board.

Abstract: An acoustic wave device includes: a substrate; a first electrode on the substrate; a piezoelectric layer on the first electrode; and a second electrode on the piezoelectric layer. A bonding interface is located between the substrate and the first electrode. The full width at half maximum (FWHM) in the X-ray diffraction pattern of the crystal plane <002> of the piezoelectric layer is between 10 arc-sec and 3600 arc-sec.

Abstract: An electronic component transfer apparatus is configured to transfer an electronic component on a flexible carrier to a target substrate. The electronic component transfer apparatus includes a first frame, a second frame, an abutting component, an actuating mechanism, an energy generating device, an image capture device, and a data processing module. The first frame is configured to carry the flexible carrier. The second frame is configured to carry the target substrate. The abutting component is disposed adjacent to the flexible carrier. The actuating mechanism is configured to actuate the abutting component, so that the abutting end of the abutting component abuts against the flexible carrier. The energy generating device generates an energy beam. The image capture device captures an image through the abutting component. The data processing module receives and computes the image to determine whether to adjust the relative position between the abutting end and the flexible carrier.

Abstract: An electronic component transferring apparatus is configured to transfer an electronic component on a flexible carrier onto a target substrate. The electronic component transferring apparatus includes a first frame configured to carry the flexible carrier, a second frame configured to carry the target substrate, an abutting component arranged adjacent to the flexible carrier, an actuating mechanism, an energy generating device, and an optical sensing module. The actuating mechanism is configured to actuate the abutting component and move the abutting component in a direction of the flexible carrier, such that an abutting end of the abutting component abuts against the flexible carrier. The energy generating device is configured to generate an energy beam penetrating at least a portion of the abutting component and being directed towards the flexible carrier from the abutting end of the abutting component. The optical sensing module is configured to perform sensing through the abutting component.

Abstract: A heat dissipating mechanism is for heat dissipation of a display module and a heat generating module of a display apparatus and includes a frame structure, a first airflow generating device, and a conductive cover structure having first, second, and third covers. The first cover is connected to the frame structure for containing the display module. The second cover has an air inlet and an air outlet and is connected to the first cover to form a channel. The third cover is connected to the second cover for containing the heat generating module. The first airflow generating device is disposed in the air inlet to guide air into the channel and out of the air outlet, so as to form an airflow for heat dissipation of the display module and the heat generating module.

Abstract: A benign tumor development trend assessment system includes an image outputting device and a server computing device. The image outputting device outputs first/second images captured from the same position in a benign tumor. The server computing device includes an image receiving module, an image pre-processing module, a target extracting module, a feature extracting module and a trend analyzing module. The image receiving module receives the first/second images. The image pre-processing module pre-processes the first/second images to obtain first/second local images. The target extracting module automatically detects and delineates tumor regions from the first/second local images to obtain first/second region of interest (ROI) images. The feature extracting module automatically identifies the first/second ROI images to obtain at least one first/second features. The trend analyzing module analyzes the first/second features to obtain a tumor development trend result.

Abstract: A circuit assembly includes an integrated circuit (IC) die and a capacitor die. The IC die has a first hybrid bonding layer. The capacitor die is stacked with the IC die, and is configured to include a capacitor coupled to the IC die, and has a second hybrid bonding layer in contact with the first hybrid bonding layer; wherein the IC die is electrically coupled to the capacitor die through the first hybrid bonding layer and the second hybrid bonding layer.

Abstract: A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.

Abstract: A circuit assembly includes an integrated circuit (IC) die and a first capacitor die. The IC die provides an IC and includes a plurality of first conductive pads. The first capacitor die provides a plurality of capacitors, and includes a plurality of second conductive pads at the first side and a plurality of conductive vias at the second side. At least one of the second conductive pads electrically connects to the capacitors. The conductive vias is adapted to form a plurality of external signal connections of the IC die and the first capacitor die. The IC die is stacked with the first capacitor die in such a way that the first conductive pads electrically connect to the second conductive pads, and surfaces of the IC die and the first capacitor die attaching to each other are substantially of the same size.