Patents by Inventor Chun Yin

Chun Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11566067
    Abstract: The present disclosure provides binding agents, such as antibodies, that specifically bind Angiopoietin-like protein 8 (ANGPTL8), including human ANGPTL8, and methods of their use.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: January 31, 2023
    Assignee: NGM Biopharmaceuticals, Inc.
    Inventors: Chun Chu, Xunshan Ding, Zhonghao Liu, Yan Wang, Yiyuan Yin, Wenwu Zhai
  • Publication number: 20230019098
    Abstract: There are provided bivalent compounds and conjugates thereof, the conjugates comprising a bivalent compound, a targeting moiety, and a bioactive agent, as well as pharmaceutical compositions and methods of use of the conjugate for the treatment, inhibition, or prevention of diseases and disorders which are therapeutic targets of the bioactive agent.
    Type: Application
    Filed: June 20, 2022
    Publication date: January 19, 2023
    Inventors: Jiasheng LV, Haixiao SIYANG, Yijie YIN, Wantao GUO, Haiming LI, Dawei CHEN, Jiamin GU, Xianqi KONG, Jun PAN, Xinxin MA, Peiming SONG, Chun WU, Hui FENG, Sheng YAO
  • Publication number: 20220415606
    Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including integrated circuit dies; measuring a position of the wafer by measuring a positions of an outer edge of the integrated circuit dies with a camera; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.
    Type: Application
    Filed: August 27, 2021
    Publication date: December 29, 2022
    Inventors: Chia-Cheng Chen, Chun-Liang Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220402236
    Abstract: The present disclosure provides for composite textiles that can include a coating layer that is compatible with textiles such as those comprising polyolefins. The coating layer, as well as the precursor coating layer composition, the coating mixture, or resin composition used to form the coating layer, include a mixture of a polyolefin resin and a thermoplastic vulcanizate (TPV). It is believed that the use of the coating layer in the disclosed composite textiles can promote better bonding between other components or materials used in articles, such as articles of footwear or articles of clothing, while resisting or preventing creasing and bagging. This allows the use of cost-effective materials such as polyolefins in the composite textiles that have adequate physical and mechanical properties, while also having sufficient chemical bonding properties.
    Type: Application
    Filed: May 10, 2022
    Publication date: December 22, 2022
    Inventors: Bhupesh Dua, Isaac Farr, Zachary C. Wright, Chih-Yin Chou, Chun-Wei Kuo
  • Publication number: 20220406629
    Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.
    Type: Application
    Filed: April 14, 2022
    Publication date: December 22, 2022
    Inventors: Chia-Cheng Chen, Chih-Kai Yang, Chun-Liang Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220406592
    Abstract: A method of forming a semiconductor device includes forming a photoresist over a target layer, where the target layer includes a substrate. The photoresist is patterned to form a patterned photoresist. Scum remains between portions of the patterned photoresist. The substrate is tilted relative to a direction of propagation of an ion beam. An ion treatment is performed on the scum. A pattern of the patterned photoresist is transferred to the target layer.
    Type: Application
    Filed: February 21, 2022
    Publication date: December 22, 2022
    Inventors: Chun-Hung Wu, Chia-Cheng Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220384269
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Publication number: 20220376087
    Abstract: The present disclosure relates to a semiconductor device including a substrate and a pair of spacers on the substrate. Each spacer of the pair of spacers includes an upper portion having a first width and a lower portion under the upper portion and having a second width different from the first width. The semiconductor device further includes a gate structure between the pair of spacers. The gate structure has an upper gate length and a lower gate length that is different from the upper gate length.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Yu KUO, Shang-Yun HUANG, Chih-Yin KUO
  • Publication number: 20220369041
    Abstract: A MEMS device and a method of manufacturing the same are provided. A semiconductor device includes a substrate; and a membrane over the substrate and configured to generate charges in response to an acoustic wave, the membrane being in a polygonal shape including vertices. The membrane includes a via pattern having first lines that partition the membrane into slices and extend to the vertices of the membrane such that the slices are separated from each other near an anchored region of the membrane and connected to each other around a central region. The via pattern further includes second lines extending from the anchored region of the membrane toward the central region of the membrane. Each of the second lines includes a length less than a length of each of the first lines.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: CHUN-WEN CHENG, CHUN YIN TSAI, CHIA-HUA CHU
  • Publication number: 20220367610
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manfacturing Co., Ltd.
    Inventors: Chen-Yin HSU, Chun Li WU, Ching-Hung KAO
  • Publication number: 20220367632
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 17, 2022
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Publication number: 20220367686
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.
    Type: Application
    Filed: November 18, 2021
    Publication date: November 17, 2022
    Inventors: Yu-Chang Lin, Liang-Yin Chen, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220367664
    Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 17, 2022
    Inventors: Yi-Chun Chen, Tsung Fan Yin, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu
  • Publication number: 20220364236
    Abstract: In an embodiment, an apparatus includes: a susceptor including substrate pockets; a gas injector disposed over the susceptor, the gas injector having first process regions, the gas injector including a first gas mixing hub and first distribution valves connecting the first gas mixing hub to the first process regions; and a controller connected to the gas injector and the susceptor, the controller being configured to: connect a first precursor material and a carrier gas to the first gas mixing hub; mix the first precursor material and the carrier gas in the first gas mixing hub to produce a first precursor gas; rotate the susceptor to rotate a first substrate disposed in one of the substrate pockets; and while rotating the susceptor, control the first distribution valves to sequentially introduce the first precursor gas at each of the first process regions as the first substrate enters each first process region.
    Type: Application
    Filed: July 14, 2022
    Publication date: November 17, 2022
    Inventors: Yung-Chang Chang, Meng-Yin Tsai, Tung-Hsiung Liu, Liang-Yu Yeh, Chun-Yi Lee, Kuo-Hsi Huang
  • Publication number: 20220367254
    Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 17, 2022
    Inventors: Yu-Shih Wang, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Chia-Cheng Chen, Liang-Yin Chen, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20220366161
    Abstract: A device detecting system is provided. The device detecting system includes a bar code scanner, a plurality of device accommodating spaces, a screen, and a server. The server obtains bar code information via the bar code scanner and opens one of the device accommodating spaces based on the bar code information to accommodate an electronic device. The server performs a test procedure on the electronic device to generate a test result, and displays the test result and operation information corresponding to the test result on the screen.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 17, 2022
    Inventors: Chien-Chih CHANG, Pei-Yin CHEN, Wei-Han LIN, Bo-Rong CHU, Yen-Ting LIU, Yu-Shen MAI, Kuan-Yu HSIAO, Chia-Hsien LIN, Pei-Yu LIAO, Chun-Yen LAI, Sheng-Yi CHEN
  • Patent number: 11502076
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Patent number: 11502161
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: November 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Yin Hsu, Chun Li Wu, Ching-Hung Kao
  • Publication number: 20220359003
    Abstract: A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Shu-Yin Ho, Hsiang-Pang Li, Yao-Wen Kang, Chun-Feng Wu, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 11494260
    Abstract: A memory with an error correction function includes a controller and a memory cell array. The controller optionally writes written data to a normal storage area and a backup area of the memory cell array, and when the controller reads first data corresponding to the written data from the normal storage area, if at least two errors are included in the first data, the controller reads the backup area to output second data corresponding to the written data from the backup area.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: November 8, 2022
    Assignee: Etron Technology, Inc.
    Inventors: Ho-Yin Chen, Ting-Feng Chang, Chun-Chia Chen