Patents by Inventor Chun Ying

Chun Ying has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12362017
    Abstract: A memory device includes a plurality of word lines (WLs) above a substrate; a plurality of memory strings laterally isolated from each other, each of the plurality of memory strings being operatively coupled to a respective subset of the plurality of WLs; and a plurality of drivers, each of the plurality of drivers being configured to control a corresponding one of the plurality of WLs and including a first transistor having a first conductive type and a second transistor having a second conductive type opposite to the first conductive type.
    Type: Grant
    Filed: April 11, 2024
    Date of Patent: July 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ying Lee, Chia-En Huang, Chieh Lee
  • Publication number: 20250218500
    Abstract: A device includes a substrate, a first sense amplifier disposed on the substrate, a first word line driver disposed on the substrate and situated adjacent the first sense amplifier in the x-direction, and a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction. A plurality of first conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array. A plurality of second conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array.
    Type: Application
    Filed: January 7, 2025
    Publication date: July 3, 2025
    Inventors: Chieh LEE, Chia-En Huang, Chun-Ying LEE, Yi-Ching LIU, Yih WANG, Hsiao Mei Tseng, Yao-Jen Yang, Jonathan Tsung-Yung Chang
  • Patent number: 12347505
    Abstract: A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.
    Type: Grant
    Filed: April 29, 2024
    Date of Patent: July 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gu-Huan Li, Tung-Cheng Chang, Perng-Fei Yuh, Chia-En Huang, Chun-Ying Lee, Yih Wang
  • Publication number: 20250182835
    Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
    Type: Application
    Filed: January 31, 2025
    Publication date: June 5, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Perng-Fei Yuh, Tung-Cheng Chang, Gu-Huan Li, Chia-En Huang, Chun-Ying Lee, Yih Wang
  • Publication number: 20250172553
    Abstract: An exemplary system and method are disclosed for a lateral flow immunoassay test designed for testing insulin efficacy and a method of using the device. The exemplary test, and associated device or system, specifically detects ineffective insulin by testing, in an insulin sample, for the presence of amyloid fibrils that may have formed from denatured insulin protein molecules. If amyloid fibrils are present, the antibodies conjugated with a label of the label-conjugated anti-amyloid fibrils (e.g., gold nanoparticles), of the test, would bind to the amyloid fibrils present in the sample to reveal a test line, or other indicator described herein, indicating the presence of amyloid fibrils. The test can employ a secondary antibody as a control line to detect the presence of insulin.
    Type: Application
    Filed: November 1, 2024
    Publication date: May 29, 2025
    Inventors: Mark Steven Nissen, Danielle Ryann Glickstein, Sierra Chun-Ying Houang, Janie Nicole Johnson, Grady Ian Mosby Lee, Charles Gilliland, Lea Gilliland
  • Publication number: 20250155472
    Abstract: A test fixture assembly is for performing a test of a DUT (Device under Test), the DUT includes a plurality of pins exposed on a surface of the DUT, and the test fixture assembly includes a circuit board and a socket unit. The circuit board includes a plurality of test pads, which are exposed on a surface of the circuit board. The socket unit includes a socket base and a plurality of socket probes, which are inserted through the socket base. A first end and a second end of each of the socket probes are respectively exposed on two opposite surfaces of the socket base. Each of the test pads, a corresponding one of the socket probes and a corresponding one of the pins are configured to be linearly arranged along a socket probe direction.
    Type: Application
    Filed: November 7, 2024
    Publication date: May 15, 2025
    Inventors: HAO LIANG HUNG, CHUN YING HUANG, KUANG TING CHI, YU CHENG LIU
  • Publication number: 20250155485
    Abstract: An antenna test assembly includes a DUT (Device under Test). The DUT includes an antenna module and a circuit board. The antenna module includes a first antenna element, which includes a first antenna pin and a second antenna pin. The circuit board includes a first line and a second line, and two ends of each of the first line and the second line are electrically connected to two metal pads, respectively, exposed on the circuit board. When the antenna test assembly is in an equipment test mode, the first line, the first antenna pin, the second antenna pin and the second line are electrically connected in sequence.
    Type: Application
    Filed: October 23, 2024
    Publication date: May 15, 2025
    Inventors: HAO LIANG HUNG, CHUN YING HUANG, YU CHENG LIU
  • Publication number: 20250118361
    Abstract: A memory device comprises a memory array, a plurality of access word lines, and a first tracking word line. The memory array may include a plurality of bit cells arranged over a plurality of rows and a plurality of columns. The plurality of access word lines may extend along a lateral direction. The plurality of rows may operatively correspond to the plurality of access word lines, respectively. The first tracking word line may also extend along the lateral direction and have a first portion extending from an edge of the memory array to a middle of the memory array and a second portion extending from the middle of the memory array to the edge of the memory array. The first combination can be different from the second combination.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ying Lee, Chieh Lee, Tung-Cheng Chang, Yen-Hsiang Huang, Chia-En Huang
  • Publication number: 20250069659
    Abstract: A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.
    Type: Application
    Filed: November 15, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih WANG, Tung-Cheng CHANG, Perng-Fei YUH, Gu-Huan LI, Chia-En HUANG, Chun-Ying LEE
  • Publication number: 20250059686
    Abstract: A knitted component comprising two yarns, forming at least a heel region of an upper for an article of footwear, where one of the yarns comprises a thermoplastic material. The outer surface may include a fused area comprising a first thermoplastic yarn. The inner surface may be at least partially formed with a second yarn and may substantially exclude the thermoplastic material. There may be a transitional area including a reduced amount of thermoplastic material relative to a fused area. The knitted component may include a cushioning material between layers of the knit element.
    Type: Application
    Filed: November 1, 2024
    Publication date: February 20, 2025
    Inventors: Jessica Green, Chun-Ying Hsu, Jaroslav J. Lupinek, Darryl Matthews, William C. McFarland, II, Chun-Yao Tu, Yi-Ning Yang, Cheng-Ying Han
  • Patent number: 12230338
    Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
    Type: Grant
    Filed: April 4, 2024
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Perng-Fei Yuh, Tung-Cheng Chang, Gu-Huan Li, Chia-En Huang, Chun-Ying Lee, Yih Wang
  • Publication number: 20250056785
    Abstract: An SRAM cell includes a first n-type channel (n-channel) layer engaged with a first gate layer to form a first device; a first p-type channel (p-channel) layer engaged with the first gate layer to form a second device, the first gate layer stacked between the first n-channel layer and the first p-channel layer along a first direction; a second n-channel layer engaged with a second gate layer to form a third device, the second gate layer coupled to a first word line and the second n-channel layer coupled to the first n-channel layer along a second direction perpendicular to the first direction; a third n-channel layer engaged with a third gate layer to form a fourth device, the third n-channel layer spaced from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer engaged with the third gate layer to form a fifth device, the third gate layer stacked between the third n-channel layer and the second p-channel layer along the fir
    Type: Application
    Filed: August 7, 2023
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Chung Chiu, Wei-Hua Chen, Chieh LEE, Chun-Ying LEE, Yi-Ching LIU, Chia-En Huang
  • Patent number: 12217790
    Abstract: A device includes a substrate, a first sense amplifier disposed on the substrate, a first word line driver disposed on the substrate and situated adjacent the first sense amplifier in the x-direction, and a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction. A plurality of first conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array. A plurality of second conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chieh Lee, Chia-En Huang, Chun-Ying Lee, Yi-Ching Liu, Yih Wang, Rose Tseng, Yao-Jen Yang, Jonathan Tsung-Yung Chang
  • Publication number: 20250024657
    Abstract: A method includes depositing a metal to form a gate layer for a first memory cell in a metallization layer of the semiconductor device. The method includes forming a plurality of semiconductor channels separated from the gate layer by a gate oxide layer. The method includes defining a plurality of gates from the gate layer. The method includes interconnecting the plurality of gates and the plurality of semiconductor channels to form a memory cell, wherein the interconnection comprises a plurality of mezzanine levels.
    Type: Application
    Filed: July 11, 2023
    Publication date: January 16, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hua Chen, Kuan-Chung Chiu, Chieh Lee, Chun-Ying Lee, Chia-En Huang, Yi-Ching Liu
  • Publication number: 20250022526
    Abstract: A circuit includes one or more functional circuits, and a clock generation circuit operatively coupled to the one or more functional circuits. The clock generation circuit is configured to: receive a control signal to switch the one or more functional circuits between a first operation mode and a second operation mode; receive a first clock signal and a second clock signal corresponding to the first operation mode and the second operation mode, respectively; and output, to the one or more functional circuits, a clock pulse signal based on either the first clock signal or the second clock signal. The clock generation circuit is configured to generate either a first conduction path to output the clock pulse signal or a second conduction path to output the clock pulse signal. Each of the first and second conduction paths includes a predefined number of gate delays.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Che Tsai, Chia-En Huang, Tung-Cheng Chang, Chun-Ying Lee, Yih Wang
  • Patent number: 12190476
    Abstract: An auto white balance adjusting method includes determining a local white pixel area and a global white pixel area, selecting a plurality of pixels of an image according to the local white pixel area for generating a local average color value in a first color space, selecting a plurality of pixels of the image according to the global white pixel area for generating a global average color value in the first color space, converting the local average color value into three primary color gains in a second color space, generating three primary color target gains according to the three primary color gains and a color temperature curve in the second color space, and adjusting a white balance of the image frame by frame to meet the three primary color target gains according to the local average color value and the three primary color gains.
    Type: Grant
    Filed: August 14, 2022
    Date of Patent: January 7, 2025
    Assignee: WELTREND SEMICONDUCTOR INC.
    Inventors: Te-Wei Hsu, Hsuan-Ying Chen, Chun-Ying Li
  • Publication number: 20250001101
    Abstract: A nebulizer includes a host, a cup body, a nozzle assembly, a nebulizing module, and an optical sensing module. The host has a detection hole. The cup body is disposed on a top of the host. The nozzle assembly is disposed on the cup body. The nozzle assembly has a nozzle. The nebulizing module is disposed on the cup body. The optical sensing module includes an optical sensor and a membrane structure. The optical sensor is disposed inside the host. The membrane structure is disposed in the detection hole, and the membrane structure blocks between the nozzle and the optical sensor. When a user inhales against the nozzle, the membrane structure is deformed by a pressure difference generated inside the nozzle, and the optical sensor is used to detect a deformation amount of the membrane structure.
    Type: Application
    Filed: June 28, 2024
    Publication date: January 2, 2025
    Inventors: CHUN-YING LI, SHIH-CHAO LUO, HSIN-YI PAI, CHIEN-SHEN TSAI
  • Patent number: 12183397
    Abstract: A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih Wang, Tung-Cheng Chang, Perng-Fei Yuh, Gu-Huan Li, Chia-En Huang, Chun-Ying Lee
  • Publication number: 20240386925
    Abstract: A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ying LEE, Chia-En Huang, Meng-Sheng Chang
  • Patent number: 12149837
    Abstract: An auto white balance adjusting method includes acquiring an image, allocating N windows inside the image according to color information of the image, filtering out M windows from the N windows for generating N-M windows according to feature information of the N windows, grouping the color temperatures of the N-M windows for generating at least one color temperature group according to a standard color temperature curve, setting a first weighting of the at least one color temperature group according to a correlation between the at least one color temperature group and the standard color temperature curve, setting a second weighting of the at least one color temperature group according to spatial information of the at least one color temperature group of the image, and adjusting a white balance of the image according to color information, the first weighting, and the second weighting.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: November 19, 2024
    Assignee: WELTREND SEMICONDUCTOR INC.
    Inventors: Chien-Ming Chen, Chun-Ying Li, Hsuan-Ying Chen, Te-Wei Hsu