Patents by Inventor Chun-Ying Yeh
Chun-Ying Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150262843Abstract: A package structure and a packaging method of wafer level chip scale package are provided. The packaging method includes: providing a carrier, and disposing a plurality of chips on the carrier; forming a plurality of adhesive layers on a surface of the corresponding chips; covering a conductive cover plate, bonding the conductive cover plate with the chips through the adhesive layers, and dividing out a plurality of packaging spaces by the conductive cover plate for disposing the chips respectively; and providing an insulation material to fill the packaging spaces through via holes on the conductive cover plate to form a first insulation structure; finally, removing the carrier.Type: ApplicationFiled: December 18, 2014Publication date: September 17, 2015Applicants: Super Group Semiconductor Co., LTD., NIKO SEMICONDUCTOR CO., LTD.Inventors: Chih-Cheng Hsieh, Hsiu-Wen Hsu, Chun-Ying Yeh, Chung-Ming Leng
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Patent number: 9035378Abstract: A trench power MOSFET structure and fabrication method thereof is provided. The fabrication method comprises following process. First, form an isolating trench. Then, form at least two doped regions around the isolating trench. The doped regions are adjacent and the doping concentrations of two doped regions are different. Form an isolating structure in the isolating trench. Wherein, the junction profiles of the two doped regions are made by on implantation method for moderate the electric field distribution and decreasing the conduction loss.Type: GrantFiled: April 21, 2014Date of Patent: May 19, 2015Assignee: SUPER GROUP SEMICONDUCTOR CO., LTD.Inventors: Hsiu-Wen Hsu, Chun-Ying Yeh, Yuan-Ming Lee
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Patent number: 8981485Abstract: A power transistor having a top-side drain and a forming method thereof are provided. Firstly, a body layer is formed. An epitaxial layer is subsequently formed on the body layer. Then a gate trench is formed in the body layer and the epitaxial layer. Afterward, a gate structure is formed in the gate trench. Then, a doped drain layer is formed within the epitaxial layer. Next, a source is formed in contact with the body layer. Lastly, a drain is formed in contact with the dope drain layer. The structure and forming method disclosed can through arranging the drain at the top of the power transistor integrate with the newly high performance packaging design structure. Accordingly, the efficiency of the power transistor can be greatly enhanced.Type: GrantFiled: August 26, 2013Date of Patent: March 17, 2015Assignee: Super Group Semiconductor Co., Ltd.Inventors: Hsiu-Wen Hsu, Chun-Ying Yeh, Yuan-Ming Lee
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Patent number: 8975691Abstract: A trenched power semiconductor device with enhanced breakdown voltage is provided. The trenched power semiconductor device has a first trench penetrating the body region located between two neighboring gate trenches. A polysilicon structure with a conductivity type identical to that of the body region is located in a lower portion of the first trench and spaced from the body region with a predetermined distance. A dielectric structure is located on the polysilicon structure and at least extended to the body region. Source regions are located in an upper portion of the body region. A heavily doped region located in the body region is extended to the bottom of the body region. A conductive structure is electrically connected to the heavily doped region and the source region.Type: GrantFiled: October 26, 2012Date of Patent: March 10, 2015Assignee: Great Power Semiconductor Corp.Inventor: Chun-Ying Yeh
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Publication number: 20140361362Abstract: A power transistor having a top-side drain and a forming method thereof are provided. Firstly, a body layer is formed. An epitaxial layer is subsequently formed on the body layer. Then a gate trench is formed in the body layer and the epitaxial layer. Afterward, a gate structure is formed in the gate trench. Then, a doped drain layer is formed within the epitaxial layer. Next, a source is formed in contact with the body layer. Lastly, a drain is formed in contact with the dope drain layer. The structure and forming method disclosed can through arranging the drain at the top of the power transistor integrate with the newly high performance packaging design structure. Accordingly, the efficiency of the power transistor can be greatly enhanced.Type: ApplicationFiled: August 26, 2013Publication date: December 11, 2014Applicant: SUPER GROUP SEMICONDUCTOR CO., LTD.Inventors: HSIU-WEN HSU, CHUN-YING YEH, YUAN-MING LEE
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Publication number: 20140349456Abstract: A trench power MOSFET structure and fabrication method thereof is provided. The fabrication method comprises following process. First, form an isolating trench. Then, form at least two doped regions around the isolating trench. The doped regions are adjacent and the doping concentrations of two doped regions are different. Form an isolating structure in the isolating trench. Wherein, the junction profiles of the two doped regions are made by on implantation method for moderate the electric field distribution and decreasing the conduction loss.Type: ApplicationFiled: April 21, 2014Publication date: November 27, 2014Applicant: SUPER GROUP SEMICONDUCTOR CO., LTD.Inventors: Hsiu-Wen HSU, Chun-Ying YEH, Yuan-Ming LEE
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Patent number: 8872266Abstract: A trench power MOSFET structure and fabrication method thereof is provided. The fabrication method comprises following process. First, form an isolating trench. Then, form at least two doped regions around the isolating trench. The doped regions are adjacent and the doping concentrations of two doped regions are different. Form an isolating structure in the isolating trench. Wherein, the junction profiles of the two doped regions are made by ion implantation method for moderate the electric field distribution and decreasing the conduction loss.Type: GrantFiled: September 12, 2013Date of Patent: October 28, 2014Assignee: Super Group Semiconductor Co., Ltd.Inventors: Hsiu-Wen Hsu, Chun-Ying Yeh, Yuan-Ming Lee
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Patent number: 8872265Abstract: An exemplary embodiment of the present disclosure illustrates a trench power MOSFET which includes a base, a plurality of first trenches, and a plurality of second trenches. The base has an active region and a termination region, wherein the termination region surrounds the active region. The plurality of first trenches is disposed in the active region. The plurality of second trenches is disposed in the termination region, wherein the second trenches extend outward from the active region side. The second trenches have isolation layers and conductive material deposited inside, in which the isolation layers are respectively disposed in the inner surface of the second trenches. The disclosed trench power MOSFET having the second trenches disposed in the termination region can increase the breakdown voltage thereof while minimize the termination region area thereby reduce the associated manufacturing cost.Type: GrantFiled: August 10, 2012Date of Patent: October 28, 2014Assignee: Great Power Semiconductor Corp.Inventors: Chun-Ying Yeh, Yuan-Ming Lee
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Patent number: 8846469Abstract: A fabrication method of a trenched power semiconductor device with source trench is provided. Firstly, at least two gate trenches are formed in a base. Then, a dielectric layer and a polysilicon structure are sequentially formed in the gate trench. Afterward, at least a source trench is formed between the neighboring gate trenches. Next, the dielectric layer and a second polysilicon structure are sequentially formed in the source trench. The second polysilicon structure is located in a lower portion of the source trench. Then, the exposed portion of the dielectric layer in the source trench is removed to expose a source region and a body region. Finally, a conductive structure is filled into the source trench to electrically connect the second polysilicon structure, the body region, and the source region.Type: GrantFiled: May 12, 2012Date of Patent: September 30, 2014Assignee: Great Power Semiconductor Corp.Inventors: Chun Ying Yeh, Hsiu Wen Hsu
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Publication number: 20140120670Abstract: A trenched power semiconductor device with enhanced breakdown voltage is provided. The trenched power semiconductor device has a first trench penetrating the body region located between two neighboring gate trenches. A polysilicon structure with a conductivity type identical to that of the body region is located in a lower portion of the first trench and spaced from the body region with a predetermined distance. A dielectric structure is located on the polysilicon structure and at least extended to the body region. Source regions are located in an upper portion of the body region. A heavily doped region located in the body region is extended to the bottom of the body region. A conductive structure is electrically connected to the heavily doped region and the source region.Type: ApplicationFiled: March 7, 2013Publication date: May 1, 2014Applicant: GREAT POWER SEMICONDUCTOR CORP.Inventor: CHUN-YING YEH
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Publication number: 20140042534Abstract: A trenched power semiconductor device with enhanced breakdown voltage is provided. The trenched power semiconductor device has a first trench penetrating the body region located between two neighboring gate trenches. A polysilicon structure with a conductivity type identical to that of the body region is located in a lower portion of the first trench and spaced from the body region with a predetermined distance. A dielectric structure is located on the polysilicon structure and at least extended to the body region. Source regions are located in an upper portion of the body region. A heavily doped region located in the body region is extended to the bottom of the body region. A conductive structure is electrically connected to the heavily doped region and the source region.Type: ApplicationFiled: October 26, 2012Publication date: February 13, 2014Applicant: GREAT POWER SEMICONDUCTOR CORP.Inventor: Chun-Ying YEH
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Publication number: 20130292761Abstract: An exemplary embodiment of the present disclosure illustrates a trench power MOSFET which includes a base, a plurality of first trenches, and a plurality of second trenches. The base has an active region and a termination region, wherein the termination region surrounds the active region. The plurality of first trenches is disposed in the active region. The plurality of second trenches is disposed in the termination region, wherein the second trenches extend outward from the active region side. The second trenches have isolation layers and conductive material deposited inside, in which the isolation layers are respectively disposed in the inner surface of the second trenches. The disclosed trench power MOSFET having the second trenches disposed in the termination region can increase the breakdown voltage thereof while minimize the termination region area thereby reduce the associated manufacturing cost.Type: ApplicationFiled: August 10, 2012Publication date: November 7, 2013Applicant: GREAT POWER SEMICONDUCTOR CORP.Inventors: CHUN YING YEH, YUAN MING LEE
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Patent number: 8525256Abstract: A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region.Type: GrantFiled: July 5, 2012Date of Patent: September 3, 2013Assignee: Great Power Semiconductor Corp.Inventors: Hsiu Wen Hsu, Chun Ying Yeh
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Patent number: 8354315Abstract: A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region.Type: GrantFiled: June 23, 2010Date of Patent: January 15, 2013Assignee: Great Power Semiconductor Corp.Inventors: Hsiu Wen Hsu, Chun Ying Yeh
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Publication number: 20120322217Abstract: A fabrication method of a trenched power semiconductor device with source trench is provided. Firstly, at least two gate trenches are formed in a base. Then, a dielectric layer and a polysilicon structure are sequentially formed in the gate trench. Afterward, at least a source trench is formed between the neighboring gate trenches. Next, the dielectric layer and a second polysilicon structure are sequentially formed in the source trench. The second polysilicon structure is located in a lower portion of the source trench. Then, the exposed portion of the dielectric layer in the source trench is removed to expose a source region and a body region. Finally, a conductive structure is filled into the source trench to electrically connect the second polysilicon structure, the body region, and the source region.Type: ApplicationFiled: May 12, 2012Publication date: December 20, 2012Applicant: GREAT POWER SEMICONDUCTOR CORP.Inventors: CHUN YING YEH, HSIU WEN HSU
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Publication number: 20120267713Abstract: A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region.Type: ApplicationFiled: July 5, 2012Publication date: October 25, 2012Applicant: GREAT POWER SEMICONDUCTOR CORP.Inventors: HSIU WEN HSU, CHUN YING YEH
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Patent number: 8283230Abstract: A fabrication method of a self-aligned power semiconductor structure is provided. Firstly, a trenched polysilicon gate is formed in a silicon substrate. Then, a self-aligned polysilicon extending structure is formed on the trenched polysilicon gate. A width of the self-aligned polysilicon extending structure is smaller than that of the trenched polysilicon gate. Thereafter, the self-aligned polysilicon extending structure is oxidized to form a silicon oxide protruding structure on the trenched polysilicon gate. Then, a first spacer is formed on a sidewall of the silicon oxide protruding structure to define a source contact window.Type: GrantFiled: June 10, 2010Date of Patent: October 9, 2012Inventor: Chun Ying Yeh
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Patent number: 8088662Abstract: A fabrication method of a trenched metal-oxide-semiconductor device is provided. Firstly, an epitaxial layer is formed on a substrate. Then, a plurality of gate trenches is formed in the epitaxial layer. Afterward, a spacer is formed on the sidewall of the trench gates. The spacer is utilized as a mask to selectively implant oxygen ion into the bottom of the gate trenches so as to form a bottom oxide layer on the bottom of the gate trenches to reduce capacitance between gate and drain.Type: GrantFiled: May 31, 2011Date of Patent: January 3, 2012Assignee: Niko Semiconductor Co., Ltd.Inventor: Chun Ying Yeh
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Publication number: 20110316077Abstract: A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region.Type: ApplicationFiled: June 23, 2010Publication date: December 29, 2011Applicant: GREAT POWER SEMICONDUCTOR CORP.Inventors: HSIU WEN HSU, CHUN YING YEH
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Publication number: 20110306194Abstract: A fabrication method of a self-aligned power semiconductor structure is provided. Firstly, a trenched polysilicon gate is formed in a silicon substrate. Then, a self-aligned polysilicon extending structure is formed on the trenched polysilicon gate. A width of the self-aligned polysilicon extending structure is smaller than that of the trenched polysilicon gate. Thereafter, the self-aligned polysilicon extending structure is oxidized to form a silicon oxide protruding structure on the trenched polysilicon gate. Then, a first spacer is formed on a sidewall of the silicon oxide protruding structure to define a source contact window.Type: ApplicationFiled: June 10, 2010Publication date: December 15, 2011Applicant: GREAT POWER SEMICONDUCTOR CORP.Inventor: Chun Ying YEH