Patents by Inventor Chun-Ying Yeh

Chun-Ying Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110230025
    Abstract: A fabrication method of a trenched metal-oxide-semiconductor device is provided. Firstly, an epitaxial layer is formed on a substrate. Then, a plurality of gate trenches is formed in the epitaxial layer. Afterward, a spacer is formed on the sidewall of the trench gates. The spacer is utilized as a mask to selectively implant oxygen ion into the bottom of the gate trenches so as to form a bottom oxide layer on the bottom of the gate trenches to reduce capacitance between gate and drain.
    Type: Application
    Filed: May 31, 2011
    Publication date: September 22, 2011
    Applicant: NIKO SEMICONDUCTOR CO., LTD.
    Inventor: CHUN YING YEH
  • Patent number: 7994001
    Abstract: A fabrication method of a trenched power semiconductor structure with a schottky diode is provided. Firstly, a drain region is formed in a substrate. Next, at least two gate structures are formed above the drain region, and then, a body and at least a source region are formed between the two adjacent gate structures. Thereafter, a first dielectric structure is formed on the gate structure to shield the gate structure. Then, a contact window is formed in the body and has side surface thereof adjacent to the source region to expose the source region. Afterward, a second dielectric structure is formed in the contact window. Next, by using the second dielectric structure as an etching mask, the body is etched to form a narrow trench extending to the drain region below the body. Finally, a metal layer is filled into the contact window and the narrow trench.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: August 9, 2011
    Assignee: Great Power Semiconductor Corp.
    Inventors: Hsiu Wen Hsu, Chun Ying Yeh
  • Patent number: 7977192
    Abstract: A fabrication method of a trenched metal-oxide-semiconductor device is provided. Firstly, an epitaxial layer is formed on a substrate. Then, a plurality of gate trenches is formed in the epitaxial layer. Afterward, a spacer is formed on the sidewall of the trench gates. The spacer is utilized as a mask to selectively implant oxygen ion into the bottom of the gate trenches so as to form a bottom oxide layer on the bottom of the gate trenches to reduce capacitance between gate and drain.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: July 12, 2011
    Assignee: Niko Semiconductor Co., Ltd.
    Inventor: Chun Ying Yeh
  • Publication number: 20100151642
    Abstract: A fabrication method of a trenched metal-oxide-semiconductor device is provided. Firstly, an epitaxial layer is formed on a substrate. Then, a plurality of gate trenches is formed in the epitaxial layer. Afterward, a spacer is formed on the sidewall of the trench gates. The spacer is utilized as a mask to selectively implant oxygen ion into the bottom of the gate trenches so as to form a bottom oxide layer on the bottom of the gate trenches to reduce capacitance between gate and drain.
    Type: Application
    Filed: August 19, 2009
    Publication date: June 17, 2010
    Applicant: NIKO SEMICONDUCTOR CO., LTD.
    Inventor: CHUN YING YEH
  • Patent number: 7538396
    Abstract: A semiconductor device includes a substrate, an epitaxial layer, a sinker, an active device, a first buried layer, and a second buried layer. The substrate has a first type conductivity. The epitaxial layer has a second type conductivity, and is located on the substrate. The sinker has the second type conductivity, and is located in the epitaxial layer. The sinker extends from the substrate to an upper surface of the epitaxial layer, and partitions a region off from the epitaxial layer. The active device is located within the region. The first buried layer has the first type conductivity, and is located between the region and the substrate. The second buried layer has the second type conductivity, and is located between the first buried layer and the substrate. The second buried layer connects with the sinker. Because of the above-mentioned configuration, latch-up can be prevented.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: May 26, 2009
    Assignee: Episil Technologies Inc.
    Inventors: Shih-Kuei Ma, Chung-Yeh Lee, Chun-Ying Yeh, Wei-Ting Kuo
  • Patent number: 7514754
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: April 7, 2009
    Assignee: Episil Technologies Inc.
    Inventors: Shih-Kuei Ma, Chung-Yeh Lee, Chun-Ying Yeh, Ker-Hsiao Huo
  • Patent number: 7411271
    Abstract: A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second sinker, a first buried layer and a second buried layer. The first and the second epitaxial layer are sequentially disposed on the substrate. The first sinker and the first buried layer separate a first region from the second epitaxial layer. The second sinker and the second buried layer separate a second region from the second epitaxial layer. The well is disposed in the first region. A first transistor is disposed in the well. A second transistor is disposed in the second region. A deep trench isolation is disposed between the first and the second region and extends from the substrate to the upper surface of the second epitaxial layer.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: August 12, 2008
    Assignee: Episil Technologies Inc.
    Inventors: Shih-Kuei Ma, Chung-Yeh Lee, Chun-Ying Yeh, Shin-Cheng Lin
  • Publication number: 20080173951
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 24, 2008
    Applicant: EPISIL TECHNOLOGIES INC.
    Inventors: Shih-Kuei Ma, Chung-Yeh Lee, Chun-Ying Yeh, Ker-Hsiao Huo
  • Publication number: 20080173949
    Abstract: A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second sinker, a first buried layer and a second buried layer. The first and the second epitaxial layer are sequentially disposed on the substrate. The first sinker and the first buried layer separate a first region from the second epitaxial layer. The second sinker and the second buried layer separate a second region from the second epitaxial layer. The well is disposed in the first region. A first transistor is disposed in the well. A second transistor is disposed in the second region. A deep trench isolation is disposed between the first and the second region and extends from the substrate to the upper surface of the second epitaxial layer.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 24, 2008
    Applicant: EPISIL TECHNOLOGIES INC.
    Inventors: Shih-Kuei Ma, Chung-Yeh Lee, Chun-Ying Yeh, Shin-Cheng Lin
  • Publication number: 20080173948
    Abstract: A semiconductor device includes a substrate, an epitaxial layer, a sinker, an active device, a first buried layer, and a second buried layer. The substrate has a first type conductivity. The epitaxial layer has a second type conductivity, and is located on the substrate. The sinker has the second type conductivity, and is located in the epitaxial layer. The sinker extends from the substrate to an upper surface of the epitaxial layer, and partitions a region off from the epitaxial layer. The active device is located within the region. The first buried layer has the first type conductivity, and is located between the region and the substrate. The second buried layer has the second type conductivity, and is located between the first buried layer and the substrate. The second buried layer connects with the sinker. Because of the above-mentioned configuration, latch-up can be prevented.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 24, 2008
    Applicant: EPISIL TECHNOLOGIES INC.
    Inventors: Shih-Kuei Ma, Chung-Yeh Lee, Chun-Ying Yeh, Wei-Ting Kuo
  • Patent number: 6129007
    Abstract: An electric automatic pop-up toaster has a carriage and a pivotably connected manually operative arm for moving the carriage to a lowermost position for toasting in well-known manner. At the beginning of each toasting cycle, the arm is horizontal and a latching plate is magnetically held down to hold the arm and the carriage in a lowermost position. The arm presses against a wire spring to hold closed a power switch (not shown) that supplies power to heating elements of the toaster. The latching plate is (magnetically) released at the end of each toasting cycle by a timer. This allows the carriage to move upwards to pop-up toasted bread in a usual way. However should the carriage fail to move upwards when the latching plate is released, the arm is pivoted by a spring and tilted to the position shown in the Figure. The wire is therefore released and enters a slot in a bracket mounted to the carriage. The switch opens and remains open to prevent power being re-instated to the heating elements.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: October 10, 2000
    Assignee: Simatelex Manufactory Co., Ltd.
    Inventors: Chi Tong Chan, Chun Ying Yeh