Abstract: Disclosed are support-activators and catalyst compositions comprising the support-activators for polymerizing olefins in which the support-activator includes a clay heteroadduct, also termed a composite, prepared from a colloidal phyllosilicate such as a colloidal smectite clay, which is chemically-modified with a surfactant. In an aspect, the clay composite can comprise the contact product of a colloidal smectite clay and a surfactant in a liquid carrier, but in the absence of any other reactant such as a cationic polymetallate, and their use as support-activators for metallocene precatalysts is also described. The use of surfactants with cationic polymetallates in forming clay-composites is also described.

Abstract: A structure may include a rotational element having a fixed central point and rotational freedom. A structure may include one or more branches connected to a tangent of the rotational element and extending outward therefrom, wherein the unit cell repeats throughout the structure; and wherein the unit cell allows rotational movement of the rotational element and prevents translational movement of the rotational element.

Abstract: A method for sharing a console variable setting of an application is applied to a plurality of electronic devices. The sharing method includes: generating, by a first electronic device, a meta file, where the meta file has setting parameters for a plurality of first setting options of a first application of the first electronic device; transforming, by the first electronic device, the meta file into a set coding image; and displaying, by the first electronic device, a display frame with the set coding image. Therefore, a second electronic device can automatically adjust setting parameters for a plurality of second setting options of a second application into setting parameters the same as those of the first application by capturing the set coding image in the display frame.

Abstract: A method includes providing a structure having a substrate and first and second semiconductor layers alternately stacked one over another above the substrate, etching the first and the second semiconductor layers to form a first continuous ring in a seal ring region of the structure, and forming an isolation structure adjacent the first continuous ring in the seal ring region. The method further includes forming a dummy gate structure that is disposed directly above the first continuous ring and completely within a boundary of the first continuous ring from a top view, growing first and second epitaxial features sandwiching the dummy gate structure, removing the dummy gate structure, resulting in a gate trench that exposes a topmost layer of the first semiconductor layers and does not expose side surfaces of the first and second semiconductor layers, and depositing a gate structure in the gate trench.

Abstract: A battery module including a plurality of battery cells, a housing in which the plurality of battery cells are accommodated, at least one cooling fin located between the plurality of battery cells in the housing, and an insulating cap for preventing direct contact between the at least one cooling fin and the housing.

Abstract: Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes a device region, an inner ring surrounding the device region, an outer ring surrounding the inner ring, a first corner area between an outer corner of the inner ring and an inner corner of the outer ring, and a second corner area disposed at an outer corner of the outer ring. The first corner area includes a first active region including a channel region and a source/drain region, a first gate structure over the channel region of the first active region, and a first source/drain contact over the source/drain region of the first active region. The first source/drain contact continuously extends from a first edge of the first corner area to a second edge of the first corner area.

Abstract: The present disclosure provides a semiconductor structure that includes a substrate having a circuit region and a seal ring region around the circuit region; first active regions of a first width W1 formed in the circuit region; second active regions of a second width W2 formed in the seal ring region; first gate stacks disposed on the first active regions in the circuit region and extending to isolation features; and second gate stacks disposed on the second active regions in the seal ring region and completely landing on the second active regions. The second width is greater than the first width, and each of the second active regions is a continuous ring shape to enclose the circuit region.

Abstract: A benzoxaborole formulation composition including a benzoxaborole, a non-ionic surfactant, or a non-ionic and ionic surfactant mixture, and a carrier is described herein. At least one of the non-ionic surfactant, the non-ionic and ionic surfactant mixture, and the carrier comprise a Lewis base or a N—H or O—H bond. The carrier is a solid or a liquid. Benzoxaborole compounds and methods of using the compounds and formulations of the compounds are described. For example, a method for reducing, preventing, ameliorating, or inhibiting an infestation by a pathogen by applying a compound or a formulation of a compound, wherein the pathogen is selected from insects, nematodes, bacteria, microbes, fungi, protozoa, viruses, and parasites, or any combinations thereof is described.

Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate. The method further includes forming contact openings on the substrate, with sidewalls of the contact openings disposed with a dielectric liner. The method further includes forming a bit line structure on the substrate, wherein the bit line structure spans the contact openings in a first direction. The dielectric liner surrounds the bit line structure within the contact openings, and the dielectric liner extends into the bit line structure above a top surface of the substrate.

Abstract: A medical image processing system includes a medical imaging device and a report generating device. The medical imaging device is configured to acquire a first image and a second image of a target part, and transmit the first image and the second image to the report generating device. The first image is used for depicting an anatomy structure of the target part, and the second image is used for depicting quantified parameter information of the target part. The report generating device is configured to identify a first region of interest (ROI) in the first image, and perform a registration for the first image and the second image to obtain a second ROI in the second image relevant to the first ROI in the first image, and further configured to generate a human readable report of the target part according to quantified parameter information corresponding to the second ROI in the second image.

Abstract: A scanner comprises a mirror, a first piezoelectric actuator, a second piezoelectric actuator, a third piezoelectric actuator, a fourth piezoelectric actuator, a first connecting member, a second connecting member, a first mirror spring, a second mirror spring, a stationary member, a first plurality of actuator springs, a second plurality of actuator springs, a third plurality of actuator springs, a fourth plurality of actuator springs, a first plurality of electrodes, and a second plurality of electrodes. The scanner is driven by piezoelectric actuators. A method of fabricating the scanner comprises the steps of providing a wafer; oxidation; deposition; patterning; and applying a singulation process.

Abstract: The present invention describes novel boron containing pyrazole compounds, or their pharmaceutically acceptable salts, pharmaceutical compositions containing them, and their medical uses. The compounds of the invention have activity as Janus kinase (JAK) inhibitors and are useful in the in the treatment or control of inflammation, auto-immune diseases, cancer, and other disorders and indications where modulation of JAK would be desirable. Also described are methods of treating inflammation, auto-immune diseases, cancer, and other conditions that are susceptible to the inhibition of a Janus kinase by administering a compound herein described.

Abstract: The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.

Abstract: A method includes rotating a wafer, dispensing a liquid from a center of the wafer to a peripheral edge of the wafer to control a temperature of the wafer, and etching an etch layer of the wafer with an etchant during or after dispensing the liquid. The liquid is dispensed through a nozzle.

Abstract: Disclosed is a flip-chip packaged power transistor module having a built-in gate driver, for outputting a high-power signal of at least tens of amperes, the module including at least one power transistor die which has an active side where at least one source pin, at least one drain pin and at least one gate pin are exposed; a ceramic substrate body which has a conducting junction side and a heat spreading side, a minimal spacing of the gate bonding pad from at least one of the source bonding pad or the drain bonding pad being less than 500 ?m, whereby parasitic inductance generated therebetween is reduced; at least one gate driver which has at least one gate pin configured to be soldered to the gate bonding pad, and at least one gate drive pin which corresponds to the gate pin and is configured to be soldered to the drive bonding pad.

Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a set of draw call instructions corresponding to a graphics workload, where the set of draw call instructions is associated with at least one run-time parameter. The apparatus may also obtain a first shader program associated with storing data in a system memory and at least one second shader program associated with storing data in a constant memory. Further, the apparatus may execute the first shader program or the at least one second shader program based on whether the at least one run-time parameter is less than or equal to a size of the constant memory. The apparatus may also update or maintain a configuration of a shader processor or a streaming processor based on executing the first shader program or the at least one second shader program.

Abstract: A multiple output voltage generator includes a voltage divider and first and second voltage converters. The voltage divider receives a power voltage and divides the power voltage to generate a first output voltage. The first and second voltage converters are coupled to the voltage divider in parallel. The first voltage converter and the second voltage converter converting the first output voltage to respectively generate a second output voltage and a third output voltage.

Abstract: Embodiments of the present disclosure relates to a wet bench processing including an in-situ pre-treatment prior to performing the first set of wet bench operations. The pre-treatment may include a pre-clean operation and/or a pre-heat operation. The pre-treatment may be performed in one of the existing ONB tanks without requiring adding new tanks to an existing wet bench tool. The pre-clean operation removes particles from a batch of wafers to avoid or reduce cross-contamination and defect issues, thus improving the yield rate of the wet bench process. The pre-heat operation provides better control and stabilize the temperature in the CHB tank to stabilize the process, such as to stabilize an etch rate.

Abstract: A display panel includes a plurality of driving electrode regions and a plurality of wiring regions connected between the driving electrode regions. A (2n-1)th wiring region extended from a (2n-1)th driving electrode region toward a (2n)th driving electrode region has a wiring extending direction forming a first included angle with an arrangement direction, and a (2n)th wiring region extended from the (2n)th driving electrode region toward a (2n+1)th driving electrode region has a wiring extending direction forming a second included angle with the arrangement direction, and a (2n+1)th wiring region extended from the (2n+1)th driving electrode region toward a (2n+2)th driving electrode region has a wiring extending direction forming a third included angle with the arrangement direction, wherein n is a positive integer. At least one of the first included angle, the second included angle and the third included angle is positive and at least one of them is negative.

Abstract: A method includes forming a semiconductor layer over a substrate; depositing a first ferroelectric layer over a channel region of the semiconductor layer; depositing a first dielectric layer over the first ferroelectric layer; depositing a second ferroelectric layer over the first dielectric layer; depositing a gate metal layer over the second ferroelectric layer; patterning the gate metal layer, the second ferroelectric layer, the first dielectric layer, and the first ferroelectric layer to form a gate structure; and forming source/drain regions in the semiconductor layer and on opposite sides of the gate structure.