Patents by Inventor Chun Yu

Chun Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12074252
    Abstract: An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure, a second type semiconductor structure, an active structure and a contact structure. The first type semiconductor structure is located on the substrate and has a first protrusion part with a first thickness and a platform part with a second thickness. The second type semiconductor structure is located on the first type semiconductor structure. The active structure is between the first type semiconductor structure and the second type semiconductor structure. The contact structure is disposed between the first type semiconductor structure and the substrate. The second thickness of the platform part is in a range of 0.01 ?m to 1 ?m.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: August 27, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chung-Hao Wang, Yu-Chi Wang, Yi-Ming Chen, Yi-Yang Chiu, Chun-Yu Lin
  • Patent number: 12067666
    Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a set of draw call instructions corresponding to a graphics workload, where the set of draw call instructions is associated with at least one run-time parameter. The apparatus may also obtain a first shader program associated with storing data in a system memory and at least one second shader program associated with storing data in a constant memory. Further, the apparatus may execute the first shader program or the at least one second shader program based on whether the at least one run-time parameter is less than or equal to a size of the constant memory. The apparatus may also update or maintain a configuration of a shader processor or a streaming processor based on executing the first shader program or the at least one second shader program.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: August 20, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Yun Du, Eric Demers, Andrew Evan Gruber, Chun Yu, Chihong Zhang, Baoguang Yang, Yuehai Du, Gang Zhong, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar
  • Publication number: 20240266437
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 8, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yu Chen, Bo-Lin Huang, Jhong-Yi Huang, Keng-Jen Lin, Yu-Shu Lin
  • Patent number: 12056790
    Abstract: The present disclosure relates to methods and apparatus for graphics processing. For example, disclosed techniques facilitate improving bindless state processing at a graphics processor. Aspects of the present disclosure can receive, at a graphics processor, a shader program including a preamble section and a main instructions section. Aspects of the present disclosure can also execute, with a scalar processor dedicated to processing preamble sections, instructions of the preamble section to implement a bindless mechanism for loading constant data associated with the shader program. Additionally, aspects of the present disclosure can distribute the main instructions section and the constant data to a streaming processor for executing the shader program.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: August 6, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Yun Du, Andrew Evan Gruber, Chun Yu, Chihong Zhang, Thomas Edwin Frisinger, Richard Hammerstone, Zilin Ying, Heng Qi, Quanquan Xu, Sheng Gu
  • Patent number: 12058124
    Abstract: Methods and systems for creating a multi-applicant account profile are described. During a first remote session, a first applicant provides at least two pieces of contact data for second applicant. A unique link and a one-time password are transmitted to the second applicant using respective first and second pieces of contact data. A second remote session is initiated, in response to receipt of the one-time password, provided via the unique link. During the second remote session, identification information of the second applicant is provided. A new multi-applicant account profile is then created, after verifying the identification information of the first applicant and the second applicant.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: August 6, 2024
    Assignee: The Toronto-Dominion Bank
    Inventors: Marina Izvekova, Jane Holtslander, Andrew David Clark, Alan Tam, Tina Patel, Steven Anthony Ghose, Michael David Mewhort, Chun Yu Zhang
  • Patent number: 12053745
    Abstract: Chemical liquid is injected into a tank. A concentration of a first gas dissolved in the chemical liquid is detected. Based on the detected concentration of the first gas, at least one of the first gas and a second gas is injected into the tank to sustain at least one of the concentration of the first gas and a concentration of the second gas in a range of a target value.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Kuo, Shang-Yun Huang, Weibo Yu, Shang-Yuan Yu
  • Patent number: 12045031
    Abstract: A thermal compensation system for machine tools includes a thermal compensation-monitoring device and a cloud processing device. The thermal compensation-monitoring device receives a plurality of temperature signals of a workpiece and corresponding processing tolerance data to build or update a thermal compensation database. The cloud processing device provides a thermal compensation model, and applies the model with the characterized temperature signals and the tolerance data to generate a compensation value so as to decide whether or not to modify the model or to run a compensation is necessary.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: July 23, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Chin Chuang, Chin-Ming Chen, Chun-Yu Tsai, Chi-Chen Lin, Chung-Kai Wu
  • Patent number: 12039125
    Abstract: A touch system is provided. The touch system includes a touch tool and a touch panel. The touch tool provides a downlink signal. The touch panel obtains a first sensing area sensed with the touch tool, and obtains a second sensing area other than the first sensing area according to the downlink signal. The touch panel provides a first uplink signal to the first sensing area, and provides a second uplink signal to the second sensing area. The first uplink signal is different from the second uplink signal. The touch tool generates a calculated uplink signal according to the first uplink signal and the second uplink signal, and provides the downlink signal according to the calculated uplink signal.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: July 16, 2024
    Assignee: ILI TECHNOLOGY CORP.
    Inventors: Chia-Yu Hung, Chun-Yu Jiang, Yifan Lin, Jui Hua Yeh, Jie-An Chen, Nai Cheng Li, Chi An Jen
  • Patent number: 12023893
    Abstract: An insulated metal substrate (IMS) and a method for manufacturing the same are disclosed. The IMS includes an electrically conductive line pattern layer, an encapsulation layer, a first adhesive layer, a second adhesive layer, and a heat sink element. The encapsulation layer fills a gap between a plurality of electrically conductive lines of the electrically conductive line pattern layer. An upper surface of the encapsulation layer is flush with an upper surface of the electrically conductive line pattern layer. The first and second adhesive layer are disposed between the electrically conductive line pattern layer and the heat sink element. A bonding strength between the first adhesive layer and the second adhesive layer is greater than 80 kg/cm2.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: July 2, 2024
    Assignee: TCLAD TECHNOLOGY CORPORATION
    Inventors: Feng-Chun Yu, Kai-Wei Lo, Wen Feng Lee, Ru-Yi Cai
  • Publication number: 20240207823
    Abstract: The present invention relates to a layered catalytic article, particularly useful for three-way conversion, which comprises a) atop layer comprising a palladium (Pd) component, a platinum (Pt) component and a rhodium (Rh) component, wherein the palladium component, the platinum component and the rhodium component are present in supported forms, and wherein at least part of the platinum component and at least part of the rhodium component are supported together on one or more supports; b) a bottom layer comprising a palladium component in a supported form as the only platinum group metal component; and c) a substrate, on which the top layer and bottom layer are carried, wherein the palladium components are loaded in the top layer and in the bottom layer at a ratio of higher than 1:1, calculated as palladium element, and also to an exhaust treatment system comprising the same.
    Type: Application
    Filed: April 20, 2022
    Publication date: June 27, 2024
    Applicant: BASF Corporation
    Inventors: Wei Liang Wang, Xiaolai Zheng, Chun Yu chen, Attilio Siani, Pascaline Tran
  • Publication number: 20240198471
    Abstract: A machine tool diagnosis method is operated in conjunction with a machine tool diagnosis system, which uses a convolutional neural network (CNN) model to analyze machining signals to generate target information including processing results and diagnosis opinions, and graphically displays a machining path of a target machining object on a display interface according to the processing results, where the display interface will further display the diagnosis opinions corresponding to the machining path.
    Type: Application
    Filed: March 8, 2023
    Publication date: June 20, 2024
    Inventors: Chi-Chen LIN, Chun-Yu TSAI, Chia-Chin CHUANG, Shao-Ku HUANG
  • Publication number: 20240204898
    Abstract: A time synchronization method for a plurality of time synchronization domains includes building a plurality of precision time protocol (PTP) instances corresponding to the plurality of time synchronization domains; determining a grandmaster clock; and synchronizing, by the plurality of PTP instances, timings of the plurality of time synchronization domains according to the grandmaster clock.
    Type: Application
    Filed: July 26, 2023
    Publication date: June 20, 2024
    Applicant: Moxa Inc.
    Inventors: Chi-Chuan Liu, Chun-Yu Lin, Chien-Yu Lai, Po-Hung Lin
  • Publication number: 20240193984
    Abstract: Provided is a full-screen display device with unit pixel having function for emitting and receiving light, including a water-oxygen barrier layer, a protective panel, a plurality of unit pixels, a light-shielding layer, and a plurality of lens. At least one of the unit pixels has a light-emitting area inside, and has a light-sensing area inside or outside. For biometrics recognition, the light-emitting area emits an incident light, which penetrates through the water-oxygen barrier layer and scatters outwardly by at least one of the lenses. The scattered incident light penetrates through the protective panel, and reflected by a test object. The reflected light penetrates through the protective panel and is converged by at least one of the lenses. The converged reflected light penetrates through the water-oxygen barrier, and the light-sensing area receives and converts the reflected light to an image electrical signal.
    Type: Application
    Filed: November 6, 2023
    Publication date: June 13, 2024
    Inventors: Chun-Yu Lee, Jun-Wen Chung
  • Publication number: 20240194128
    Abstract: Provided is a full-screen display device having different unit pixels for emitting and receiving light, including a water-oxygen barrier layer, a protective panel, a plurality of unit pixels, a light-shielding layer, and a plurality of lenses. When the device performs biometric recognition, at least one unit pixel is defined as a light-emitting element, at least one unit pixel is defined as a sensing element, and the sensing element has a light-sensing area. The light-emitting element emits an incident light to penetrate the water-oxygen barrier layer and scatter outwardly by at least one lens. The scattered incident light penetrates the protective panel, and then reflected by a test object, followed by penetrating the protective panel, and entering at least one lens, which converges the reflected light. The converged light penetrates the water-oxygen barrier layer to be received by the light-sensing area and converted into an image electrical signal.
    Type: Application
    Filed: October 25, 2023
    Publication date: June 13, 2024
    Inventors: Chun-Yu Lee, Jun-Wen Chung
  • Publication number: 20240186447
    Abstract: The present disclosure provides a light-emitting device comprising a substrate with a topmost surface; a first semiconductor stack arranged on the substrate, and comprising a first top surface separated from the topmost surface by a first distance; a first bonding layer arranged between the substrate and the first semiconductor stack; a second semiconductor stack arranged on the substrate, and comprising a second top surface separated from the topmost surface by a second distance which is different form the first distance; a second bonding layer arranged between the substrate and the second semiconductor stack; a third semiconductor stack arranged on the substrate, and comprising third top surface separated from the topmost surface by a third distance; and a third bonding layer arranged between the substrate and the third semiconductor stack; wherein the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are configured to emit different color lights.
    Type: Application
    Filed: February 12, 2024
    Publication date: June 6, 2024
    Inventors: Chien-Fu HUANG, Chih-Chiang LU, Chun-Yu LIN, Hsin-Chih CHIU
  • Publication number: 20240181116
    Abstract: An air sterilization device for plumbing air ventilation piping and a system therefor with sensors, network connectivity, monitoring and controlling. The air sterilization device is disposed coaxially with a plumbing ventilating pipe to ensure air escaping out from the ventilating pipe has been sterilized.
    Type: Application
    Filed: February 16, 2022
    Publication date: June 6, 2024
    Inventors: Ronald Chun Yu Lam, Louis Chi Hung Lam
  • Publication number: 20240179065
    Abstract: An auto-configuration method for a time-sensitive networking (TSN) system includes obtaining, by a first OPC UA client module, a TSN configuration of a stream; transmitting, by the first OPC UA client module, the TSN configuration to an OPC UA server module of a centralized user configuration (CUC) in the TSN system; obtaining, by the CUC, a routing information and scheduling of the stream according to the TSN configuration and a network topology; sending, by the first OPC UA client module, a request to the OPC UA server to obtain the routing information and scheduling of the stream; and configuring the routing information and scheduling of the stream to a plurality of end stations in the TSN system after the plurality of end stations are online.
    Type: Application
    Filed: October 16, 2023
    Publication date: May 30, 2024
    Applicant: Moxa Inc.
    Inventors: Yueh-Ming Ko, Chun-Yu Lin, Tzu-Lun Huang
  • Publication number: 20240176734
    Abstract: The invention relates to an apparatus for searching for logical address ranges of host commands. The first comparator outputs logic “0” to the NOR gate when a first end logical address is not smaller than a second start logical address. The second comparator outputs logic “0” to the NOR gate when a second end logical address is not smaller than a first start logical address. The NOR gate outputs logic “1” to a matching register and an output circuitry when receiving logic “0” from both the first and the second comparators. The output circuitry outputs a memory address of a random access memory (RAM) storing a second logical address range from the second start logical address to the second end logical address to a resulting address register when receiving logic “1” from the NOR gate.
    Type: Application
    Filed: September 15, 2023
    Publication date: May 30, 2024
    Applicant: Silicon Motion, Inc.
    Inventor: Chun-Yu CHEN
  • Patent number: 11990547
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: May 21, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yu Chen, Bo-Lin Huang, Jhong-Yi Huang, Keng-Jen Lin, Yu-Shu Lin
  • Publication number: 20240161968
    Abstract: A planar transformer is configured on a multi-layer circuit board of a resonant converter. The planar transformer includes multiple layers of primary-side traces, multiple layers of secondary-side traces, and an iron core. The primary-side traces serve as a primary-side coil of the transformer to generate a first direction magnetic flux when the resonant converter operates. The secondary-side traces serve as a secondary-side coil of the transformer to generate a second direction magnetic flux when the resonant converter operates. The primary-side traces and the secondary-side traces surround a first core pillar and the second core pillar, and the primary-side traces and the secondary-side traces are configured in a specific stacked structure on the multi-layer circuit board, so that a magnetomotive force of the planar transformer can maintain balance during the operation of the resonant converter.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Hsun CHIU, Yi-Sheng CHANG, Chun-Yu YANG, Meng-Chi TSAI