Patents by Inventor Chun-Yuan Chou
Chun-Yuan Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916100Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.Type: GrantFiled: March 21, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
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Publication number: 20230251140Abstract: The present disclosure provides a microbolometer including a substrate, a readout circuit layer disposed above the substrate, a first vanadium oxide layer disposed above the readout circuit layer, a second vanadium oxide layer disposed on the first vanadium oxide layer, and an infrared absorbing layer disposed above the second vanadium oxide layer, in which an oxygen content of the second vanadium oxide is higher than that of the first vanadium oxide layer.Type: ApplicationFiled: March 18, 2022Publication date: August 10, 2023Inventor: Chun-Yuan CHOU
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Patent number: 11171134Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.Type: GrantFiled: December 19, 2019Date of Patent: November 9, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
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Publication number: 20200126985Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
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Patent number: 10522544Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.Type: GrantFiled: May 1, 2019Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
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Publication number: 20190259753Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.Type: ApplicationFiled: May 1, 2019Publication date: August 22, 2019Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
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Patent number: 10312236Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.Type: GrantFiled: November 27, 2017Date of Patent: June 4, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
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Patent number: 10170417Abstract: A semiconductor structure includes a substrate, a dielectric layer, a metal layer, and a tungsten layer. The dielectric layer is on the substrate and has a recess feature therein. The metal layer is in the recess feature. The metal layer has an oxygen content less than about 0.1 atomic percent. The tungsten layer is in the recess feature and in contact with the metal layer.Type: GrantFiled: November 19, 2017Date of Patent: January 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Chiang Wu, Chia-Ching Lee, Hsueh-Wen Tsau, Chun-Yuan Chou, Cheng-Yen Tsai, Da-Yuan Lee, Ming-Hsing Tsai
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Patent number: 9935173Abstract: Structures and formation methods of a semiconductor device structure are provided. A method for forming a semiconductor device structure includes patterning a semiconductor substrate to form a fin structure. The method also includes forming a sacrificial material over the fin structure. The method further includes forming spacer elements adjoining sidewalls of the sacrificial material. Furthermore, the method includes removing the sacrificial material so that a trench is formed between the spacer elements. The method also includes forming a gate dielectric layer in the trench. The method further includes forming a work function layer in the trench to cover the gate dielectric layer. In addition, the method includes depositing a tungsten bulk layer with a precursor to fill the trench. The precursor includes a tungsten-containing material that is substantially free of fluoride.Type: GrantFiled: November 29, 2016Date of Patent: April 3, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Chiang Wu, Chia-Ching Lee, Hsueh-Wen Tsau, Chun-Yuan Chou, Ching-Hwanq Su
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Publication number: 20180090431Abstract: A semiconductor structure includes a substrate, a dielectric layer, a metal layer, and a tungsten layer. The dielectric layer is on the substrate and has a recess feature therein. The metal layer is in the recess feature. The metal layer has an oxygen content less than about 0.1 atomic percent. The tungsten layer is in the recess feature and in contact with the metal layer.Type: ApplicationFiled: November 19, 2017Publication date: March 29, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Chiang WU, Chia-Ching LEE, Hsueh-Wen TSAU, Chun-Yuan CHOU, Cheng-Yen TSAI, Da-Yuan LEE, Ming-Hsing TSAI
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Publication number: 20180076198Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.Type: ApplicationFiled: November 27, 2017Publication date: March 15, 2018Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
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Patent number: 9831243Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.Type: GrantFiled: July 27, 2015Date of Patent: November 28, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Da-Yuan Lee, Kuang-Yuan Hsu, Jeff J. Xu
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Patent number: 9824969Abstract: A semiconductor structure and the method of forming the same are provided. The method of forming a semiconductor structure includes forming a recess feature in a basal layer, forming a metal layer on the basal layer, exposing the metal layer to a tungsten halide gas to form an oxygen-deficient metal layer, and forming a bulk tungsten layer on the oxygen-deficient metal layer.Type: GrantFiled: May 14, 2016Date of Patent: November 21, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Chiang Wu, Chia-Ching Lee, Hsueh-Wen Tsau, Chun-Yuan Chou, Cheng-Yen Tsai, Da-Yuan Lee, Ming-Hsing Tsai
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Publication number: 20170330829Abstract: A semiconductor structure and the method of forming the same are provided. The method of forming a semiconductor structure includes forming a recess feature in a basal layer, forming a metal layer on the basal layer, exposing the metal layer to a tungsten halide gas to form an oxygen-deficient metal layer, and forming a bulk tungsten layer on the oxygen-deficient metal layer.Type: ApplicationFiled: May 14, 2016Publication date: November 16, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Chiang WU, Chia-Ching LEE, Hsueh-Wen TSAU, Chun-Yuan CHOU, Cheng-Yen TSAI, Da-Yuan LEE, Ming-Hsing TSAI
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Patent number: 9761683Abstract: A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. An interlayer insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so that a space is formed. A gate dielectric layer is formed in the space. A first metal layer is formed over the gate dielectric in the space. A second metal layer is formed over the first metal layer in the space. The first and second metal layers are partially removed, thereby reducing a height of the first and second metal layers. A third metal layer is formed over the partially removed first and second metal layers.Type: GrantFiled: May 15, 2015Date of Patent: September 12, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Yuan Chou, Chung-Chiang Wu, Da-Yuan Lee, Weng Chang
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Publication number: 20160336420Abstract: A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. An interlayer insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so that a space is formed. A gate dielectric layer is formed in the space. A first metal layer is formed over the gate dielectric in the space. A second metal layer is formed over the first metal layer in the space. The first and second metal layers are partially removed, thereby reducing a height of the first and second metal layers. A third metal layer is formed over the partially removed first and second metal layers.Type: ApplicationFiled: May 15, 2015Publication date: November 17, 2016Inventors: Chun-Yuan CHOU, Chung-Chiang WU, Da-Yuan LEE, Weng CHANG
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Patent number: 9449828Abstract: An aspect of this description relates to a method that includes partially filling an opening in a dielectric material with a high-dielectric-constant material. The method also includes partially filling the opening with a first metal material over the high-dielectric-constant material. The method further includes filling the opening with a capping layer over the first metal material. The method additionally includes partially removing the first metal material and the capping layer in the opening using a wet etching process in a solution including one or more of H2O2, NH4OH, HCl, H2SO4 or diluted HF. The method also includes fully removing the remaining capping layer in the opening using a wet etching process in a solution includes one or more of NH4OH or diluted HF. The method further includes depositing a second metal material in the opening over the remaining first metal material.Type: GrantFiled: November 10, 2015Date of Patent: September 20, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hao Hou, Peng-Soon Lim, Da-Yuan Lee, Xiong-Fei Yu, Chun-Yuan Chou, Fan-Yi Hsu, Jian-Hao Chen, Kuang-Yuan Hsu
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Publication number: 20160064223Abstract: An aspect of this description relates to a method that includes partially filling an opening in a dielectric material with a high-dielectric-constant material. The method also includes partially filling the opening with a first metal material over the high-dielectric-constant material. The method further includes filling the opening with a capping layer over the first metal material. The method additionally includes partially removing the first metal material and the capping layer in the opening using a wet etching process in a solution including one or more of H2O2, NH4OH, HCl, H2SO4 or diluted HF. The method also includes fully removing the remaining capping layer in the opening using a wet etching process in a solution includes one or more of NH4OH or diluted HF. The method further includes depositing a second metal material in the opening over the remaining first metal material.Type: ApplicationFiled: November 10, 2015Publication date: March 3, 2016Inventors: Cheng-Hao HOU, Peng-Soon LIM, Da-Yuan LEE, Xiong-Fei YU, Chun-Yuan CHOU, Fan-Yi HSU, Jian-Hao CHEN, Kuang-Yuan HSU
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Patent number: 9196691Abstract: A method of fabricating a metal gate electrode of a field effect transistor includes forming a dielectric layer over an active region, and forming an opening in the dielectric layer. The method further includes partially filling the opening with a high-dielectric-constant material, partially filling the opening with a conformal first metal material over the high-dielectric-constant material, and filling the opening with a capping layer over the first metal material. The method further includes partially removing the first metal material and capping layer in the opening using a wet etching process. The method further includes fully removing the remaining capping layer in the opening using a wet etching process. The method further includes depositing a second metal material in the opening over the remaining first metal material, and planarizing the second metal material.Type: GrantFiled: September 4, 2013Date of Patent: November 24, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hao Hou, Peng-Soon Lim, Da-Yuan Lee, Xiong-Fei Yu, Chun-Yuan Chou, Fan-Yi Hsu, Jian-Hao Chen, Kuang-Yuan Hsu
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Publication number: 20150333064Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.Type: ApplicationFiled: July 27, 2015Publication date: November 19, 2015Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Da-Yuan Lee, Kuang-Yuan Hsu, Jeff J. Xu