Patents by Inventor Chun-Yuan Chou

Chun-Yuan Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10401980
    Abstract: A mouse device with a button feedback mechanism is provided. The mouse device includes a mouse body and a button module. The mouse body includes an upper case, a lower case and a hollow cylinder. The button module includes a button, an elastic element, an attracting element and a suspension arm. The elastic element is disposed within the hollow cylinder and located under the pressing part. The button is contacted with the elastic element. The attracting element is installed on the upper case. The suspension arm includes a connection segment and a free segment. The connection segment is penetrated through the hollow cylinder and connected with the elastic element. The free segment is located under the attracting element. Consequently, the mouse device provides the sound feedback and the touch feedback.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 3, 2019
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Yung-Ming Tsai, Chun-Che Wu, Yi-Te Chou, Chung-Yuan Chen
  • Publication number: 20190259753
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
  • Patent number: 10312236
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
  • Publication number: 20190146600
    Abstract: A mouse device with a button feedback mechanism is provided. The mouse device includes a mouse body and a button module. The mouse body includes an upper case, a lower case and a hollow cylinder. The button module includes a button, an elastic element, an attracting element and a suspension arm. The elastic element is disposed within the hollow cylinder and located under the pressing part. The button is contacted with the elastic element. The attracting element is installed on the upper case. The suspension arm includes a connection segment and a free segment. The connection segment is penetrated through the hollow cylinder and connected with the elastic element. The free segment is located under the attracting element. Consequently, the mouse device provides the sound feedback and the touch feedback.
    Type: Application
    Filed: February 27, 2018
    Publication date: May 16, 2019
    Inventors: Yung-Ming Tsai, Chun-Che Wu, Yi-Te Chou, Chung-Yuan Chen
  • Patent number: 10170417
    Abstract: A semiconductor structure includes a substrate, a dielectric layer, a metal layer, and a tungsten layer. The dielectric layer is on the substrate and has a recess feature therein. The metal layer is in the recess feature. The metal layer has an oxygen content less than about 0.1 atomic percent. The tungsten layer is in the recess feature and in contact with the metal layer.
    Type: Grant
    Filed: November 19, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Hsueh-Wen Tsau, Chun-Yuan Chou, Cheng-Yen Tsai, Da-Yuan Lee, Ming-Hsing Tsai
  • Patent number: 9935173
    Abstract: Structures and formation methods of a semiconductor device structure are provided. A method for forming a semiconductor device structure includes patterning a semiconductor substrate to form a fin structure. The method also includes forming a sacrificial material over the fin structure. The method further includes forming spacer elements adjoining sidewalls of the sacrificial material. Furthermore, the method includes removing the sacrificial material so that a trench is formed between the spacer elements. The method also includes forming a gate dielectric layer in the trench. The method further includes forming a work function layer in the trench to cover the gate dielectric layer. In addition, the method includes depositing a tungsten bulk layer with a precursor to fill the trench. The precursor includes a tungsten-containing material that is substantially free of fluoride.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Hsueh-Wen Tsau, Chun-Yuan Chou, Ching-Hwanq Su
  • Publication number: 20180090431
    Abstract: A semiconductor structure includes a substrate, a dielectric layer, a metal layer, and a tungsten layer. The dielectric layer is on the substrate and has a recess feature therein. The metal layer is in the recess feature. The metal layer has an oxygen content less than about 0.1 atomic percent. The tungsten layer is in the recess feature and in contact with the metal layer.
    Type: Application
    Filed: November 19, 2017
    Publication date: March 29, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Chiang WU, Chia-Ching LEE, Hsueh-Wen TSAU, Chun-Yuan CHOU, Cheng-Yen TSAI, Da-Yuan LEE, Ming-Hsing TSAI
  • Publication number: 20180076198
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Application
    Filed: November 27, 2017
    Publication date: March 15, 2018
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
  • Patent number: 9831243
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Da-Yuan Lee, Kuang-Yuan Hsu, Jeff J. Xu
  • Patent number: 9824969
    Abstract: A semiconductor structure and the method of forming the same are provided. The method of forming a semiconductor structure includes forming a recess feature in a basal layer, forming a metal layer on the basal layer, exposing the metal layer to a tungsten halide gas to form an oxygen-deficient metal layer, and forming a bulk tungsten layer on the oxygen-deficient metal layer.
    Type: Grant
    Filed: May 14, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Hsueh-Wen Tsau, Chun-Yuan Chou, Cheng-Yen Tsai, Da-Yuan Lee, Ming-Hsing Tsai
  • Publication number: 20170330829
    Abstract: A semiconductor structure and the method of forming the same are provided. The method of forming a semiconductor structure includes forming a recess feature in a basal layer, forming a metal layer on the basal layer, exposing the metal layer to a tungsten halide gas to form an oxygen-deficient metal layer, and forming a bulk tungsten layer on the oxygen-deficient metal layer.
    Type: Application
    Filed: May 14, 2016
    Publication date: November 16, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Chiang WU, Chia-Ching LEE, Hsueh-Wen TSAU, Chun-Yuan CHOU, Cheng-Yen TSAI, Da-Yuan LEE, Ming-Hsing TSAI
  • Patent number: 9761683
    Abstract: A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. An interlayer insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so that a space is formed. A gate dielectric layer is formed in the space. A first metal layer is formed over the gate dielectric in the space. A second metal layer is formed over the first metal layer in the space. The first and second metal layers are partially removed, thereby reducing a height of the first and second metal layers. A third metal layer is formed over the partially removed first and second metal layers.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chou, Chung-Chiang Wu, Da-Yuan Lee, Weng Chang
  • Publication number: 20160336420
    Abstract: A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. An interlayer insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so that a space is formed. A gate dielectric layer is formed in the space. A first metal layer is formed over the gate dielectric in the space. A second metal layer is formed over the first metal layer in the space. The first and second metal layers are partially removed, thereby reducing a height of the first and second metal layers. A third metal layer is formed over the partially removed first and second metal layers.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 17, 2016
    Inventors: Chun-Yuan CHOU, Chung-Chiang WU, Da-Yuan LEE, Weng CHANG
  • Patent number: 9449828
    Abstract: An aspect of this description relates to a method that includes partially filling an opening in a dielectric material with a high-dielectric-constant material. The method also includes partially filling the opening with a first metal material over the high-dielectric-constant material. The method further includes filling the opening with a capping layer over the first metal material. The method additionally includes partially removing the first metal material and the capping layer in the opening using a wet etching process in a solution including one or more of H2O2, NH4OH, HCl, H2SO4 or diluted HF. The method also includes fully removing the remaining capping layer in the opening using a wet etching process in a solution includes one or more of NH4OH or diluted HF. The method further includes depositing a second metal material in the opening over the remaining first metal material.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hao Hou, Peng-Soon Lim, Da-Yuan Lee, Xiong-Fei Yu, Chun-Yuan Chou, Fan-Yi Hsu, Jian-Hao Chen, Kuang-Yuan Hsu
  • Publication number: 20160064223
    Abstract: An aspect of this description relates to a method that includes partially filling an opening in a dielectric material with a high-dielectric-constant material. The method also includes partially filling the opening with a first metal material over the high-dielectric-constant material. The method further includes filling the opening with a capping layer over the first metal material. The method additionally includes partially removing the first metal material and the capping layer in the opening using a wet etching process in a solution including one or more of H2O2, NH4OH, HCl, H2SO4 or diluted HF. The method also includes fully removing the remaining capping layer in the opening using a wet etching process in a solution includes one or more of NH4OH or diluted HF. The method further includes depositing a second metal material in the opening over the remaining first metal material.
    Type: Application
    Filed: November 10, 2015
    Publication date: March 3, 2016
    Inventors: Cheng-Hao HOU, Peng-Soon LIM, Da-Yuan LEE, Xiong-Fei YU, Chun-Yuan CHOU, Fan-Yi HSU, Jian-Hao CHEN, Kuang-Yuan HSU
  • Patent number: 9196691
    Abstract: A method of fabricating a metal gate electrode of a field effect transistor includes forming a dielectric layer over an active region, and forming an opening in the dielectric layer. The method further includes partially filling the opening with a high-dielectric-constant material, partially filling the opening with a conformal first metal material over the high-dielectric-constant material, and filling the opening with a capping layer over the first metal material. The method further includes partially removing the first metal material and capping layer in the opening using a wet etching process. The method further includes fully removing the remaining capping layer in the opening using a wet etching process. The method further includes depositing a second metal material in the opening over the remaining first metal material, and planarizing the second metal material.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: November 24, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hao Hou, Peng-Soon Lim, Da-Yuan Lee, Xiong-Fei Yu, Chun-Yuan Chou, Fan-Yi Hsu, Jian-Hao Chen, Kuang-Yuan Hsu
  • Publication number: 20150333064
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Application
    Filed: July 27, 2015
    Publication date: November 19, 2015
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Da-Yuan Lee, Kuang-Yuan Hsu, Jeff J. Xu
  • Patent number: 9105624
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: August 11, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Da-Yuan Lee, Kuang-Yuan Hsu, Jeff J. Xu
  • Publication number: 20150017796
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Application
    Filed: September 26, 2014
    Publication date: January 15, 2015
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Da-Yuan Lee, Kuang-Yuan Hsu, Jeff J. Xu
  • Patent number: D852151
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: June 25, 2019
    Assignee: ZIPPY TECHNOLOGY CORP.
    Inventors: Chin-Wen Chou, Yung-Hsin Huang, Yu-Yuan Chang, Yung-Feng Chiu, Chun-Lung Su, Chih-Hao Chen