Patents by Inventor Chun-Yuan Lo

Chun-Yuan Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240129012
    Abstract: A wearable device includes a frame element and a dielectric substrate. The frame element includes a first metal element, a second metal element, and a third metal element. A first gap is provided between the first metal element and the second metal element. A second gap is provided between the second metal element and the third metal element. A third gap is provided between the third metal element and the first metal element. The dielectric substrate is surrounded by the first metal element, the second metal element, and the third metal element. A first antenna element is formed by the first metal element. A second antenna element is formed by the second metal element. A third antenna element is formed by the third metal element.
    Type: Application
    Filed: December 6, 2022
    Publication date: April 18, 2024
    Inventors: Jing-Yao XU, Chung-Ting HUNG, Chun-Yuan WANG, Chu-Yu TANG, Yi-Chih LO, Yu-Chen ZHAO, Chih-Tsung TSENG
  • Patent number: 11929434
    Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: March 12, 2024
    Assignee: eMemory Technology Inc.
    Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
  • Publication number: 20240055053
    Abstract: A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 15, 2024
    Inventors: Chia-Jung HSU, Chun-Yuan LO, Chun-Hsiao LI, Chang-Chun LUNG
  • Publication number: 20240056080
    Abstract: A level shifter includes a cross-coupled transistor pair, first through third cascode transistor pairs and a differential input pair sequentially coupled in series, and further includes a sub level shifter. The first cascode transistor pair is controlled by a first reference voltage. The second cascode transistor pair is controlled by a pair of differential control voltages. The third cascode transistor pair is controlled by a second reference voltage lower than the first reference voltage. The differential input pair is controlled by a pair of differential input voltages. The sub level shifter generates the differential control voltages according to the differential input voltages and the first and second reference voltages. The differential control voltages are switched between the first and second reference voltages. The level shifter outputs a pair of differential output voltages through inverted and non-inverted output terminals coupled with the second cascode transistor pair.
    Type: Application
    Filed: August 8, 2023
    Publication date: February 15, 2024
    Inventors: Chun-Yuan LO, Wu-Chang CHANG, Bo-Chang LI
  • Publication number: 20230052438
    Abstract: A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.
    Type: Application
    Filed: June 14, 2022
    Publication date: February 16, 2023
    Inventors: Tsung-Mu LAI, Chun-Yuan LO, Chun-Chieh CHAO
  • Publication number: 20220246758
    Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.
    Type: Application
    Filed: April 15, 2022
    Publication date: August 4, 2022
    Applicant: eMemory Technology Inc.
    Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
  • Patent number: 11398259
    Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: July 26, 2022
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Hsin Chen, Chun-Yuan Lo, Shih-Chen Wang, Tsung-Mu Lai
  • Patent number: 11335805
    Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: May 17, 2022
    Assignee: eMemory Technology Inc.
    Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
  • Patent number: 11164880
    Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 2, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chih-Hsin Chen, Wei-Ren Chen
  • Publication number: 20210287746
    Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.
    Type: Application
    Filed: February 24, 2021
    Publication date: September 16, 2021
    Inventors: Chih-Hsin CHEN, Chun-Yuan LO, Shih-Chen WANG, Tsung-Mu LAI
  • Publication number: 20210074855
    Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 11, 2021
    Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
  • Publication number: 20200006508
    Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.
    Type: Application
    Filed: March 29, 2019
    Publication date: January 2, 2020
    Inventors: Chun-Yuan LO, Shih-Chen WANG, Wen-Hao CHING, Chih-Hsin CHEN, Wei-Ren CHEN
  • Patent number: 10181342
    Abstract: A method for improving a program speed of a memory includes acquiring a program level of the memory, comparing the program level of the memory with a valid level and a target level for generating a comparison result, and entering a first loop and/or a second loop for setting a program voltage of the memory according to the comparison result.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: January 15, 2019
    Assignee: eMemory Technology Inc.
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chun-Chieh Chao
  • Publication number: 20180315462
    Abstract: A method for improving a program speed of a memory includes acquiring a program level of the memory, comparing the program level of the memory with a valid level and a target level for generating a comparison result, and entering a first loop and/or a second loop for setting a program voltage of the memory according to the comparison result.
    Type: Application
    Filed: November 3, 2017
    Publication date: November 1, 2018
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chun-Chieh Chao
  • Patent number: 9953685
    Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, a memory device, and a select transistor. The memory device is located on the substrate. The select transistor is located on the substrate and electrically connected to the memory device. The select transistor includes a select gate, a first dielectric layer, and a second dielectric layer. The select gate is located on the substrate. The first dielectric layer is adjacent to the second dielectric layer, and located between the select gate and the substrate. The first dielectric layer is closer to the memory device than the second dielectric layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: April 24, 2018
    Assignee: eMemory Technology Inc.
    Inventors: Jui-Ming Kuo, Chun-Yuan Lo, Chia-Jung Hsu, Wein-Town Sun
  • Patent number: 9792993
    Abstract: A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: October 17, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching
  • Publication number: 20170206969
    Abstract: A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.
    Type: Application
    Filed: January 16, 2017
    Publication date: July 20, 2017
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching
  • Patent number: 9653173
    Abstract: A memory cell includes a coupling device, a read transistor, a first read selection transistor, a second read selection transistor, an erase device, a program transistor, and a program selection transistor. The coupling device is formed on a first doped region. The erase device is formed on a second doped region. The read transistor, the first read selection transistor, the second read selection transistor, the program transistor, and the program selection transistor are formed on a third doped region. A gate terminal of the coupling device is coupled to a common floating gate. A gate terminal of the erase device is coupled to the floating gate. During a program operation, electrical charges are moved from the common floating gate. During an erase operation, electrical charges are ejected from the common floating gate to the erase device.
    Type: Grant
    Filed: December 4, 2016
    Date of Patent: May 16, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Chun-Yuan Lo, Wei-Chen Chang, Shih-Chen Wang
  • Patent number: 9484094
    Abstract: A control method of a resistive random-access memory is provided. Firstly, an action is performed on the resistive random-access memory, so that the resistive random-access memory has a specified state. Then, an operation period begins. During a first sub-period of the operation period, a first control signal with a first polarity is provided. During a second sub-period of the operation period, a second control signal with a second polarity is provided. During a third sub-period of the operation period, a third control signal with the first polarity is provided. During a fourth sub-period of the operation period, a read signal is provided, so that the resistive random-access memory generates a read current. According to the read current, a controlling circuit verifies whether the resistive random-access memory is in the specified state.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: November 1, 2016
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chia-Jung Hsu, Wein-Town Sun, Chun-Yuan Lo
  • Patent number: 9424939
    Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: August 23, 2016
    Assignee: eMemory Technology Inc.
    Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo