Patents by Inventor Chun-Yuan Lo
Chun-Yuan Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11164880Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.Type: GrantFiled: March 29, 2019Date of Patent: November 2, 2021Assignee: EMEMORY TECHNOLOGY INC.Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chih-Hsin Chen, Wei-Ren Chen
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Publication number: 20210287746Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.Type: ApplicationFiled: February 24, 2021Publication date: September 16, 2021Inventors: Chih-Hsin CHEN, Chun-Yuan LO, Shih-Chen WANG, Tsung-Mu LAI
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Publication number: 20210074855Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.Type: ApplicationFiled: September 8, 2020Publication date: March 11, 2021Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
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Publication number: 20200006508Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.Type: ApplicationFiled: March 29, 2019Publication date: January 2, 2020Inventors: Chun-Yuan LO, Shih-Chen WANG, Wen-Hao CHING, Chih-Hsin CHEN, Wei-Ren CHEN
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Patent number: 10181342Abstract: A method for improving a program speed of a memory includes acquiring a program level of the memory, comparing the program level of the memory with a valid level and a target level for generating a comparison result, and entering a first loop and/or a second loop for setting a program voltage of the memory according to the comparison result.Type: GrantFiled: November 3, 2017Date of Patent: January 15, 2019Assignee: eMemory Technology Inc.Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chun-Chieh Chao
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Publication number: 20180315462Abstract: A method for improving a program speed of a memory includes acquiring a program level of the memory, comparing the program level of the memory with a valid level and a target level for generating a comparison result, and entering a first loop and/or a second loop for setting a program voltage of the memory according to the comparison result.Type: ApplicationFiled: November 3, 2017Publication date: November 1, 2018Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chun-Chieh Chao
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Patent number: 9953685Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, a memory device, and a select transistor. The memory device is located on the substrate. The select transistor is located on the substrate and electrically connected to the memory device. The select transistor includes a select gate, a first dielectric layer, and a second dielectric layer. The select gate is located on the substrate. The first dielectric layer is adjacent to the second dielectric layer, and located between the select gate and the substrate. The first dielectric layer is closer to the memory device than the second dielectric layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.Type: GrantFiled: September 5, 2014Date of Patent: April 24, 2018Assignee: eMemory Technology Inc.Inventors: Jui-Ming Kuo, Chun-Yuan Lo, Chia-Jung Hsu, Wein-Town Sun
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Patent number: 9792993Abstract: A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.Type: GrantFiled: January 16, 2017Date of Patent: October 17, 2017Assignee: eMemory Technology Inc.Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching
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Publication number: 20170206969Abstract: A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.Type: ApplicationFiled: January 16, 2017Publication date: July 20, 2017Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching
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Patent number: 9653173Abstract: A memory cell includes a coupling device, a read transistor, a first read selection transistor, a second read selection transistor, an erase device, a program transistor, and a program selection transistor. The coupling device is formed on a first doped region. The erase device is formed on a second doped region. The read transistor, the first read selection transistor, the second read selection transistor, the program transistor, and the program selection transistor are formed on a third doped region. A gate terminal of the coupling device is coupled to a common floating gate. A gate terminal of the erase device is coupled to the floating gate. During a program operation, electrical charges are moved from the common floating gate. During an erase operation, electrical charges are ejected from the common floating gate to the erase device.Type: GrantFiled: December 4, 2016Date of Patent: May 16, 2017Assignee: eMemory Technology Inc.Inventors: Chun-Yuan Lo, Wei-Chen Chang, Shih-Chen Wang
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Patent number: 9484094Abstract: A control method of a resistive random-access memory is provided. Firstly, an action is performed on the resistive random-access memory, so that the resistive random-access memory has a specified state. Then, an operation period begins. During a first sub-period of the operation period, a first control signal with a first polarity is provided. During a second sub-period of the operation period, a second control signal with a second polarity is provided. During a third sub-period of the operation period, a third control signal with the first polarity is provided. During a fourth sub-period of the operation period, a read signal is provided, so that the resistive random-access memory generates a read current. According to the read current, a controlling circuit verifies whether the resistive random-access memory is in the specified state.Type: GrantFiled: October 1, 2015Date of Patent: November 1, 2016Assignee: EMEMORY TECHNOLOGY INC.Inventors: Chia-Jung Hsu, Wein-Town Sun, Chun-Yuan Lo
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Patent number: 9424939Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.Type: GrantFiled: October 23, 2015Date of Patent: August 23, 2016Assignee: eMemory Technology Inc.Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo
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Publication number: 20160211020Abstract: A control method of a resistive random-access memory is provided. Firstly, an action is performed on the resistive random-access memory, so that the resistive random-access memory has a specified state. Then, an operation period begins. During a first sub-period of the operation period, a first control signal with a first polarity is provided. During a second sub-period of the operation period, a second control signal with a second polarity is provided. During a third sub-period of the operation period, a third control signal with the first polarity is provided. During a fourth sub-period of the operation period, a read signal is provided, so that the resistive random-access memory generates a read current. According to the read current, a controlling circuit verifies whether the resistive random-access memory is in the specified state.Type: ApplicationFiled: October 1, 2015Publication date: July 21, 2016Inventors: Chia-Jung Hsu, Wein-Town Sun, Chun-Yuan Lo
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Publication number: 20160148686Abstract: A memory cell array includes a first bit line, a first word line, a first source line pair and a first memory cell. A select terminal of the first memory cell is connected with the first word line. A first control terminal of the first memory cell is connected with a first source line of the first source line pair. A second control terminal of the first memory cell is connected with a second source line of the first source line pair. A third control terminal of the first memory cell is connected with the first bit line.Type: ApplicationFiled: October 7, 2015Publication date: May 26, 2016Inventors: Chia-Jung Hsu, Wein-Town Sun, Ching-Sung Yang, Chi-Yi Shao, Chun-Yuan Lo, Yu-Hsiung Tsai, Ching-Yuan Lin
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Publication number: 20160042795Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.Type: ApplicationFiled: October 23, 2015Publication date: February 11, 2016Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo
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Patent number: 9196367Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.Type: GrantFiled: June 4, 2014Date of Patent: November 24, 2015Assignee: eMemory Technology Inc.Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo
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Publication number: 20150287467Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.Type: ApplicationFiled: June 4, 2014Publication date: October 8, 2015Applicant: eMemory Technology Inc.Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo
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Publication number: 20150287738Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, a memory device, and a select transistor. The memory device is located on the substrate. The select transistor is located on the substrate and electrically connected to the memory device. The select transistor includes a select gate, a first dielectric layer, and a second dielectric layer. The select gate is located on the substrate. The first dielectric layer is adjacent to the second dielectric layer, and located between the select gate and the substrate. The first dielectric layer is closer to the memory device than the second dielectric layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.Type: ApplicationFiled: September 5, 2014Publication date: October 8, 2015Inventors: Jui-Ming Kuo, Chun-Yuan Lo, Chia-Jung Hsu, Wein-Town Sun
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Patent number: 8927370Abstract: A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.Type: GrantFiled: July 24, 2006Date of Patent: January 6, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Yuan Lo, Chun-Pei Wu
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Patent number: 8526240Abstract: A programming method includes the following steps. A preset programming voltage is applied to a memory cell to program the memory cell. A first verify voltage is applied to the memory cell to detect a programming result of the memory cell. A programming voltage applied on the memory cell is adjusted according to the programming result of the memory cell. A flash memory is also provided.Type: GrantFiled: August 17, 2011Date of Patent: September 3, 2013Assignee: eMemory Technology Inc.Inventors: Chun-Yuan Lo, Wein-Town Sun