Patents by Inventor Chun-Yuan Lo

Chun-Yuan Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160042795
    Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.
    Type: Application
    Filed: October 23, 2015
    Publication date: February 11, 2016
    Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo
  • Patent number: 9196367
    Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: November 24, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo
  • Publication number: 20150287467
    Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.
    Type: Application
    Filed: June 4, 2014
    Publication date: October 8, 2015
    Applicant: eMemory Technology Inc.
    Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo
  • Publication number: 20150287738
    Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, a memory device, and a select transistor. The memory device is located on the substrate. The select transistor is located on the substrate and electrically connected to the memory device. The select transistor includes a select gate, a first dielectric layer, and a second dielectric layer. The select gate is located on the substrate. The first dielectric layer is adjacent to the second dielectric layer, and located between the select gate and the substrate. The first dielectric layer is closer to the memory device than the second dielectric layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.
    Type: Application
    Filed: September 5, 2014
    Publication date: October 8, 2015
    Inventors: Jui-Ming Kuo, Chun-Yuan Lo, Chia-Jung Hsu, Wein-Town Sun
  • Patent number: 8927370
    Abstract: A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: January 6, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chun-Yuan Lo, Chun-Pei Wu
  • Patent number: 8526240
    Abstract: A programming method includes the following steps. A preset programming voltage is applied to a memory cell to program the memory cell. A first verify voltage is applied to the memory cell to detect a programming result of the memory cell. A programming voltage applied on the memory cell is adjusted according to the programming result of the memory cell. A flash memory is also provided.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: September 3, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Chun-Yuan Lo, Wein-Town Sun
  • Patent number: 8451641
    Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: May 28, 2013
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
  • Publication number: 20130044548
    Abstract: A flash memory and a memory cell programming method thereof are provided. The programming method includes the following steps. A preset programming voltage is applied to a memory cell to program the memory cell. A first verify voltage is applied to the memory cell to detect a programming result of the memory cell. A programming voltage applied on the memory cell is adjusted according to the programming result of the memory cell.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 21, 2013
    Applicant: EMEMORY TECHNOLOGY INC.
    Inventors: Chun-Yuan Lo, Wein-Town Sun
  • Publication number: 20120273842
    Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line.
    Type: Application
    Filed: July 13, 2012
    Publication date: November 1, 2012
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
  • Patent number: 8243489
    Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: August 14, 2012
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
  • Publication number: 20110156102
    Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.
    Type: Application
    Filed: March 10, 2011
    Publication date: June 30, 2011
    Applicant: MACRONIX International Co., Ltd.
    Inventors: CHUN-YUAN LO, Cheng-Ming Yih, Wen-Pin Lu
  • Patent number: 7924591
    Abstract: A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: April 12, 2011
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
  • Publication number: 20100202179
    Abstract: A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line.
    Type: Application
    Filed: February 6, 2009
    Publication date: August 12, 2010
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
  • Publication number: 20080020525
    Abstract: A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.
    Type: Application
    Filed: July 24, 2006
    Publication date: January 24, 2008
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Yuan Lo, Chun-Pei Wu