Patents by Inventor Chun-Yuan Lo
Chun-Yuan Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9424939Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.Type: GrantFiled: October 23, 2015Date of Patent: August 23, 2016Assignee: eMemory Technology Inc.Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo
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Publication number: 20160211020Abstract: A control method of a resistive random-access memory is provided. Firstly, an action is performed on the resistive random-access memory, so that the resistive random-access memory has a specified state. Then, an operation period begins. During a first sub-period of the operation period, a first control signal with a first polarity is provided. During a second sub-period of the operation period, a second control signal with a second polarity is provided. During a third sub-period of the operation period, a third control signal with the first polarity is provided. During a fourth sub-period of the operation period, a read signal is provided, so that the resistive random-access memory generates a read current. According to the read current, a controlling circuit verifies whether the resistive random-access memory is in the specified state.Type: ApplicationFiled: October 1, 2015Publication date: July 21, 2016Inventors: Chia-Jung Hsu, Wein-Town Sun, Chun-Yuan Lo
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Publication number: 20160148686Abstract: A memory cell array includes a first bit line, a first word line, a first source line pair and a first memory cell. A select terminal of the first memory cell is connected with the first word line. A first control terminal of the first memory cell is connected with a first source line of the first source line pair. A second control terminal of the first memory cell is connected with a second source line of the first source line pair. A third control terminal of the first memory cell is connected with the first bit line.Type: ApplicationFiled: October 7, 2015Publication date: May 26, 2016Inventors: Chia-Jung Hsu, Wein-Town Sun, Ching-Sung Yang, Chi-Yi Shao, Chun-Yuan Lo, Yu-Hsiung Tsai, Ching-Yuan Lin
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Publication number: 20160042795Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.Type: ApplicationFiled: October 23, 2015Publication date: February 11, 2016Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo
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Patent number: 9196367Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.Type: GrantFiled: June 4, 2014Date of Patent: November 24, 2015Assignee: eMemory Technology Inc.Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo
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Publication number: 20150287467Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.Type: ApplicationFiled: June 4, 2014Publication date: October 8, 2015Applicant: eMemory Technology Inc.Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo
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Publication number: 20150287738Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, a memory device, and a select transistor. The memory device is located on the substrate. The select transistor is located on the substrate and electrically connected to the memory device. The select transistor includes a select gate, a first dielectric layer, and a second dielectric layer. The select gate is located on the substrate. The first dielectric layer is adjacent to the second dielectric layer, and located between the select gate and the substrate. The first dielectric layer is closer to the memory device than the second dielectric layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.Type: ApplicationFiled: September 5, 2014Publication date: October 8, 2015Inventors: Jui-Ming Kuo, Chun-Yuan Lo, Chia-Jung Hsu, Wein-Town Sun
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Patent number: 8927370Abstract: A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.Type: GrantFiled: July 24, 2006Date of Patent: January 6, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Yuan Lo, Chun-Pei Wu
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Patent number: 8526240Abstract: A programming method includes the following steps. A preset programming voltage is applied to a memory cell to program the memory cell. A first verify voltage is applied to the memory cell to detect a programming result of the memory cell. A programming voltage applied on the memory cell is adjusted according to the programming result of the memory cell. A flash memory is also provided.Type: GrantFiled: August 17, 2011Date of Patent: September 3, 2013Assignee: eMemory Technology Inc.Inventors: Chun-Yuan Lo, Wein-Town Sun
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Patent number: 8451641Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line.Type: GrantFiled: July 13, 2012Date of Patent: May 28, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
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Publication number: 20130044548Abstract: A flash memory and a memory cell programming method thereof are provided. The programming method includes the following steps. A preset programming voltage is applied to a memory cell to program the memory cell. A first verify voltage is applied to the memory cell to detect a programming result of the memory cell. A programming voltage applied on the memory cell is adjusted according to the programming result of the memory cell.Type: ApplicationFiled: August 17, 2011Publication date: February 21, 2013Applicant: EMEMORY TECHNOLOGY INC.Inventors: Chun-Yuan Lo, Wein-Town Sun
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Publication number: 20120273842Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line.Type: ApplicationFiled: July 13, 2012Publication date: November 1, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
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Patent number: 8243489Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.Type: GrantFiled: March 10, 2011Date of Patent: August 14, 2012Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
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Publication number: 20110156102Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.Type: ApplicationFiled: March 10, 2011Publication date: June 30, 2011Applicant: MACRONIX International Co., Ltd.Inventors: CHUN-YUAN LO, Cheng-Ming Yih, Wen-Pin Lu
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Patent number: 7924591Abstract: A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line.Type: GrantFiled: February 6, 2009Date of Patent: April 12, 2011Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
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Publication number: 20100202179Abstract: A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line.Type: ApplicationFiled: February 6, 2009Publication date: August 12, 2010Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
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Publication number: 20080020525Abstract: A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.Type: ApplicationFiled: July 24, 2006Publication date: January 24, 2008Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chun-Yuan Lo, Chun-Pei Wu