Patents by Inventor Chunchieh Huang

Chunchieh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190221781
    Abstract: An evaporator and a method for adjusting levelness of an evaporator are provided. The evaporator includes: a first platform; a second platform; a distance measuring assembly configured to measure a plurality of first distances between the first platform and a top of a vacuum chamber accommodating the evaporator, and/or a plurality of second distances between the first platform and the second platform; a driving assembly configured to drive the first platform and/or the second platform; and a data processing assembly electrically connected to the distance measuring assembly and the driving assembly, and configured to control the driving assembly to adjust levelness of the first platform according to the measured plurality of first distances, and/or to control the driving assembly to adjust levelness of the second platform according to the measured plurality of second distances.
    Type: Application
    Filed: August 23, 2018
    Publication date: July 18, 2019
    Inventors: Chunchieh Huang, Chunsheng Gu, Xin Zhao
  • Publication number: 20190203335
    Abstract: The present disclosure provides a mask plate frame. The mask plate frame includes two opposite rims, and a plurality of connectors detachably mounted to a first surface of each rim along a length direction of each rim. Each connector is used to mount a mask strip.
    Type: Application
    Filed: August 3, 2018
    Publication date: July 4, 2019
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Shouhua LV, Chunchieh HUANG, Baojun LI
  • Publication number: 20190185984
    Abstract: The disclosure relates to the field of vapor-plating technologies, and discloses a mask strip, a mask, and a vapor-plating device to thereby improve the quality of vapor plating. The mask strip includes solder holes for soldering on a upper surface of a frame of a mask, and a first groove which is on the sides of the solder holes away from the upper surface of the frame, and communicates with the solder holes.
    Type: Application
    Filed: August 3, 2018
    Publication date: June 20, 2019
    Inventors: Chunchieh Huang, Shouhua Lv
  • Publication number: 20190062895
    Abstract: A mask plate and a method for fabricating the same are disclosed. The mask plate includes a frame, mask strips fixed to the frame and extending in a first direction, and shielding strips having a same extending direction as that of the mask strips. The shielding strips are arranged in space between neighboring mask strips and shield a gap between neighboring mask strips. Each shielding strip includes a first border parallel with the first direction. Each shielding strip is provided with a first location hole at both ends of its extending direction. Some or all of the shielding strips have widths in a direction perpendicular to the first direction which are different from one another. Distances between centers of the first location holes of each shielding strip and the first border of the shielding strips lie in a first threshold range.
    Type: Application
    Filed: August 31, 2018
    Publication date: February 28, 2019
    Inventors: Jian ZHANG, Zhiming LIN, Chunchieh HUANG, Qi WANG
  • Publication number: 20190054655
    Abstract: The present disclosure provides a cement sintering device and a cement sintering method. The cement sintering device comprises an emitting module configured to emit laser to an irradiation area corresponding to the emitting module; a moving module configured to control the irradiation area of the emitting module to move so that the irradiation area covers a cement to be sintered and is moved along an extension direction of the cement; a detecting module configured to detect structural information about the cement covered by the irradiation area; and a control module configured to adjust operation parameters of the emitting module for emitting the laser based on the structural information. Based on the solution of the present disclosure, it is possible to achieve the effect of more accurately sintering.
    Type: Application
    Filed: May 24, 2018
    Publication date: February 21, 2019
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Liang ZHANG, Xu CHEN, Chunchieh HUANG, Shanshan BAO
  • Publication number: 20180312396
    Abstract: Systems and methods are provided that provide a getter in a micromechanical system. In some embodiments, a microelectromechanical system (MEMS) is bonded to a substrate. The MEMS and the substrate have a first cavity and a second cavity therebetween. A first getter is provided on the substrate in the first cavity and integrated with an electrode. A second getter is provided in the first cavity over a passivation layer on the substrate. In some embodiments, the first cavity is a gyroscope cavity, and the second cavity is an accelerometer cavity.
    Type: Application
    Filed: April 26, 2017
    Publication date: November 1, 2018
    Inventors: Daesung Lee, Jeff Chunchieh Huang, Jongwoo Shin, Bongsang Kim, Logeeswaran Veerayah Jayaraman
  • Publication number: 20180222745
    Abstract: Methods and systems for MEMS devices with dual damascene formed electrodes is disclosed and may include forming first and second dielectric layers on a semiconductor substrate that includes a conductive layer at least partially covered by the first dielectric layer; removing a portion of the second dielectric layer; forming vias through the second dielectric layer and at least a portion of the second dielectric layer, where the via extends to the conductive layer; forming electrodes by filling the vias and a volume that is the removed portion of the second dielectric layer with a first metal; and coupling a micro-electro-mechanical systems (MEMS) substrate to the semiconductor substrate. A third dielectric layer may be formed between the first and second dielectric layers. A metal pad may be formed on at least one electrode by depositing a second metal on the electrode and removing portions of the second metal, which may be aluminum.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 9, 2018
    Inventors: Chunchieh Huang, Peter Smeys
  • Publication number: 20180209029
    Abstract: The embodiments of the present disclosure provide a mask assembly, an installation method thereof and an evaporation apparatus. The mask assembly includes: a support frame; a mask fixed on the support frame, the mask including an active mask region and an inactive mask region surrounding the active mask region; and a first support bar fixed on the support frame. The first support bar is disposed on a side of the mask facing away from the support frame, a projection of the first support bar onto a plane where the support frame is located is overlapped with a projection of the mask onto the plane where the support frame is located by a first overlapping portion, and the first overlapping portion is located within a projection area of the inactive mask region onto the plane where the support frame is located.
    Type: Application
    Filed: May 17, 2017
    Publication date: July 26, 2018
    Inventors: Zhiming Lin, Zhen Wang, Jian Zhang, Fuqiang Tang, Chunchieh Huang
  • Patent number: 9919915
    Abstract: Methods and systems for MEMS devices with dual damascene formed electrodes is disclosed and may include forming first and second dielectric layers on a semiconductor substrate that includes a conductive layer at least partially covered by the first dielectric layer; removing a portion of the second dielectric layer; forming vias through the second dielectric layer and at least a portion of the second dielectric layer, where the via extends to the conductive layer; forming electrodes by filling the vias and a volume that is the removed portion of the second dielectric layer with a first metal; and coupling a micro-electro-mechanical systems (MEMS) substrate to the semiconductor substrate. A third dielectric layer may be formed between the first and second dielectric layers. A metal pad may be formed on at least one electrode by depositing a second metal on the electrode and removing portions of the second metal, which may be aluminum.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: March 20, 2018
    Assignee: INVENSENSE, INC.
    Inventors: Chunchieh Huang, Peter Smeys
  • Publication number: 20180052007
    Abstract: A device and method for a MEMS device with at least one sensor is disclosed. A thermal element is disposed in the MEMS device to selectively adjust a temperature of the MEMS device. A calibration operation is initiated for the sensor to determine a correction value to be applied to the sensor measurement based on the temperature. The correction value is stored.
    Type: Application
    Filed: October 30, 2017
    Publication date: February 22, 2018
    Inventors: WESLEY JAMES EMMANOUEL TESKEY, NIM HAK TEA, BONGSANG KIM, CHUNCHIEH HUANG
  • Publication number: 20170355593
    Abstract: Methods and systems for MEMS devices with dual damascene formed electrodes is disclosed and may include forming first and second dielectric layers on a semiconductor substrate that includes a conductive layer at least partially covered by the first dielectric layer; removing a portion of the second dielectric layer; forming vias through the second dielectric layer and at least a portion of the second dielectric layer, where the via extends to the conductive layer; forming electrodes by filling the vias and a volume that is the removed portion of the second dielectric layer with a first metal; and coupling a micro-electro-mechanical systems (MEMS) substrate to the semiconductor substrate. A third dielectric layer may be formed between the first and second dielectric layers. A metal pad may be formed on at least one electrode by depositing a second metal on the electrode and removing portions of the second metal, which may be aluminum.
    Type: Application
    Filed: June 14, 2016
    Publication date: December 14, 2017
    Inventors: Chunchieh Huang, Peter Smeys
  • Patent number: 9391169
    Abstract: Provided is a TFT with an improved gate insulator, having an insulator substrate, a gate layer, a gate insulator layer, a active semiconductor layer, and a source and drain electrode layer, wherein the gate insulator layer includes a first silicon nitride film, a second silicon nitride film disposed on the first silicon nitride film and a third silicon nitride film disposed on the second silicon nitride, and compared to the second silicon nitride film, each of the first silicon nitride film and the third silicon nitride film is much thinner and has a lower content of N—H bond. Also provided is a display including said TFTs. According to the present disclosure, an improved gate insulator layer capable of withstanding higher voltage can be achieved due to the laminated structure and accordingly a TFT with excellent reliability can be formed.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: July 12, 2016
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventors: Weiting Chen, Chunchieh Huang
  • Patent number: 9379357
    Abstract: The present application discloses an OLED with an improved structure, comprising a reflective anode layer, a transparent cathode layer, an organic light-emitting layer sandwiched between the anode layer and the cathode layer, and a side reflective layer surrounding the organic light-emitting layer and forming a light exiting area together with the anode layer, wherein the light emitted from the light-emitting layer is reflected by both of the anode layer and the side reflective layer, and then leaves from the light exiting area. According to the present disclosure, the lateral light is reflected by the side reflective layer arranged around the organic light-emitting layer, such that the luminescent efficiency of the OLED with said improved structure can be significantly increased.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: June 28, 2016
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventors: Chihhung Liu, Chenghsien Wang, Chunchieh Huang
  • Publication number: 20160118239
    Abstract: The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a third silicon nitride film having a third thickness and a third content of N—H bonds, disposed on the second silicon nitride film; wherein both the first thickness and the third thickness are less than the second thickness, both the N—H bonds in the first content and the third content are less than that in the second N—H bonds content, and a difference of the N—H bonds between the third content and the first content is no less than 5%. The present disclosure also provides a method for forming the above gate insulating layer.
    Type: Application
    Filed: January 6, 2016
    Publication date: April 28, 2016
    Inventors: Wei-ting CHEN, Chia-chi HUANG, Chunchieh HUANG, Youyuan HU
  • Patent number: 9224957
    Abstract: The present disclosure provides a method for measuring an offset of a sub-pixel in an OLED manufacturing process, including: depositing OLED material onto a display unit in a substrate through a hollow portion of a mask, the display unit including an effective region and a peripheral measuring region at periphery of the effective region, the OLED material forming a plurality of effective sub-pixels within the effective region and forming a plurality of dummy sub-pixels within the peripheral measuring region; and using UV light to excite at least a portion of the dummy sub-pixels of the OLED material to emit light, and measuring the offset of the dummy sub-pixel with respect to a predetermined position of a corresponding light emitting unit located on the substrate.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: December 29, 2015
    Inventors: ChiaPin Kang, Chin Chih Lin, Chunchieh Huang
  • Publication number: 20150129989
    Abstract: The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a third silicon nitride film having a third thickness and a third content of N—H bonds, disposed on the second silicon nitride film; wherein both the first thickness and the third thickness are less than the second thickness, both the N—H bonds in the first content and the third content are less than that in the second N—H bonds content, and a difference of the N—H bonds between the third content and the first content is no less than 5%. The present disclosure also provides a method for forming the above gate insulating layer.
    Type: Application
    Filed: August 19, 2014
    Publication date: May 14, 2015
    Inventors: Wei-ting CHEN, Chia-chi HUANG, Chunchieh HUANG, Youyuan HU
  • Publication number: 20140361265
    Abstract: The present application discloses an OLED with an improved structure, comprising a reflective anode layer, a transparent cathode layer, an organic light-emitting layer sandwiched between the anode layer and the cathode layer, and a side reflective layer surrounding the organic light-emitting layer and forming a light exiting area together with the anode layer, wherein the light emitted from the light-emitting layer is reflected by both of the anode layer and the side reflective layer, and then leaves from the light exiting area. According to the present disclosure, the lateral light is reflected by the side reflective layer arranged around the organic light-emitting layer, such that the luminescent efficiency of the OLED with said improved structure can be significantly increased.
    Type: Application
    Filed: December 12, 2013
    Publication date: December 11, 2014
    Applicant: EverDisplay Optronics (Shanghai) Limited
    Inventors: Chihhung LIU, Chenghsien WANG, Chunchieh HUANG
  • Publication number: 20140353689
    Abstract: Provided is a TFT with an improved gate insulator, having an insulator substrate, a gate layer, a gate insulator layer, a active semiconductor layer, and a source and drain electrode layer, wherein the gate insulator layer includes a first silicon nitride film, a second silicon nitride film disposed on the first silicon nitride film and a third silicon nitride film disposed on the second silicon nitride, and compared to the second silicon nitride film, each of the first silicon nitride film and the third silicon nitride film is much thinner and has a lower content of N—H bond. Also provided is a display including said TFTs. According to the present disclosure, an improved gate insulator layer capable of withstanding higher voltage can be achieved due to the laminated structure and accordingly a TFT with excellent reliability can be formed.
    Type: Application
    Filed: February 19, 2014
    Publication date: December 4, 2014
    Applicant: EverDisplay Optronics (Shanghai) Limited
    Inventors: Weiting CHEN, Chunchieh HUANG
  • Patent number: 7910429
    Abstract: Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: March 22, 2011
    Assignee: ProMOS Technologies, Inc.
    Inventors: Zhong Dong, Chuck Jang, Ching-Hwa Chen, Chunchieh Huang, Jin-Ho Kim, Vei-Han Chan, Chung Wai Leung, Chia-Shun Hsiao, George Kovall, Steven Ming Yang
  • Patent number: 7387942
    Abstract: Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: June 17, 2008
    Assignee: ProMOS Technologies Inc.
    Inventors: Daniel Wang, Chunchieh Huang, Dong Jun Kim