Abstract: Disclosed are apparatuses, methods, and manufacturing methods relating to improving data retention in nonvolatile memory. In many embodiments, monitor reference currents in addition to a normal reference current are used to determine whether to refresh the data memory.

Abstract: A method for programming a multi-level-cell NAND flash memory device having plural memory cells is disclosed to reduce the programming time. The method comprises: programming each memory cell to a zero state, programming from the zero state to a first state by activating a first program signal and programming from the zero state to a quasi-second state and a semi-third state by activating a second program signal, programming from the quasi-second state to a second state and programming from the semi-third state to a quasi-third state by activating the second program signal, and programming from the quasi-third state to a third state by activating the first program signal. The present invention also discloses a page buffer to perform the method for programming a multi-level-cell NAND flash memory device, which comprises a bit line selection circuit, a first register, a second register, a first verify circuit, a second verify circuit and an exclusion circuit.

Abstract: A method for reading a NAND flash memory device having plural normal cells, which utilizes plural reference bit lines associated with plural reference cells to read the normal cells in one phase to reduce the read time, is disclosed. The method comprises ramping up a selected word line voltage in a predetermined period and reading the normal cells with a zero state, a first state, a second state and a third state in the predetermined period. The present invention also discloses a memory cell array concerning the method for reading a NAND flash memory device.

Abstract: A non-volatile memory device with a page buffer having dual registers includes a memory cell array, a selector circuit and a page buffer circuit, the selector circuit being coupled to an exterior data line, the page buffer circuit including a first register and a second register being coupled between the memory cell array and the selector circuit, and the first register and second register being commonly coupled through a sense node. The first and second registers alternately write data to the memory cell array for programming. As one of the first and second registers performs programming, the other register stores data from the data line concurrently. In other words, the second register stores data from the data line when the first register is in programming, whereas the first register stores data from the data line when the second register is in programming.

Abstract: A light diffusion module and a back light module using the same. The light diffusion module is disposed corresponding to the light source module of the back light module. The light diffusion module includes a first diffusion layer and the second diffusion layer. The first diffusion layer is disposed on top of the light source module and the top light exit surface has a plurality of first micro structures juxtapositioned to each other. The second diffusion layer is disposed on top of the first diffusion layer, and the top surface has a plurality of second micro structures juxtapositioned to each other. The ratio of the width of each first micro structure to the width of each second micro structure is between 1.1 and 1.8. The ratio of the height of each first micro structure to the height of each second micro structure is between 0.8 and 1.

Abstract: A method for preparing a gate oxide layer is described. First, a trench surrounding an active area is formed in a substrate, and a dielectric block is then formed in the trench such that an upper surface of the dielectric block is not aligned with that of the substrate. Subsequently, an ion implantation process is performed to implant nitrogen-containing dopants into the substrate in the active area, and a thermal oxidation process is then performed to form a gate oxide layer on the surface of the substrate in the active area. Particularly, the concentration of the nitrogen-containing dopants at the center of the active area is higher than that at the edge of the active area. The nitrogen-containing dopants inhibit the reaction rate of the thermal oxidation process, so as to prevent the gate oxide layer from thinning at the edge near the trench.

Abstract: The present invention discloses a scheduling method for remote object procedure call and system thereof, by a two-phase scheduling mechanism to deal with the stateful and stateless invocations simultaneously. First, plural stateful invocations in a workflow are grouped into plural groups of stateful tasks. Then, the groups of stateful tasks are assigned to the server with the minimum load. Next, the rank of each of the stateful and stateless invocations is determined to form a scheduling sequence. An estimated finish time for each stateless invocation for each server is calculated and the stateless invocation is assigned to the server with the minimum estimated finish time.

Abstract: A method of automatically determining a sensing timing in a page buffer of a NAND flash memory device is disclosed, which includes the steps of discharging a first reference bit line, discharging a second reference bit line, determining a first control signal and determining a second control signal. To perform the method, an apparatus of automatically determining a sensing timing in a page buffer of a NAND flash memory device is also disclosed. The apparatus includes a first reference bit line, a first current sink, a first reference page buffer, the second reference bit line, a second current sink and a second reference page buffer. The first reference bit line is coupled to the first current sink and the first reference page buffer at both ends thereof. The second reference bit line is coupled to the second current sink and the second reference page buffer at both ends thereof.

Abstract: A sliding module comprises a sliding member having a transversal plate disposed transversally and coupled vertically at a substantially middle position of two sliding plates, and the transversal plate includes a rectangular transversal groove, and the transversal groove includes a through hole disposed at an external side of the transversal groove; a spindle member being a rectangular spindle plate and includes a spindle hole disposed separately on both sides of the spindle member, and a spindle bolt passes through one of said spindle holes and is coupled to the transversal groove; a tension spring with both ends separately including a spring hook and one of the spring hooks is latched into the through hole, and another spring hook is latched into a bolt aperture of a spindle bolt above the transversal groove; and a slid member being a driven plate with both lateral sides bent into a sliding groove for embedding an external side of the sliding plate, and the driven plate includes a plate aperture for passing

Abstract: A roller device for attaching to a shaft of a treadmill, includes a tubular housing having two carriers engaged in the end portions, and the carriers each includes a casing directly folded from the end portion of the housing, and two bearing members are engaged in the casings of the carriers, for engaging with the shaft, and for smoothly and rotatably attaching the housing to the shaft, and for allowing the roller device to be easily and readily attached to treadmills. The casing includes an outer peripheral flap formed integral with the housing, and includes an outer diameter smaller than an inner diameter of the housing, for resiliently supporting the casing within the housing.

Abstract: A process is implemented to form a contact opening in a semiconductor device that includes a gate electrode on a substrate, a spacer on a sidewall of the gate electrode and a dielectric material covering the gate electrode. The process comprises forming a photoresist pattern on a surface of the dielectric material, etching the dielectric material until the bottom liner layer is exposed, forming a protective layer on a sidewall of the spacer while etching the dielectric material, and etching the bottom liner layer.

Abstract: A rotation-type safety buckle comprising of a male fastener and a female fastener is provided. The male fastener has a column at a center of an inner surface thereof, the male fastener has a respective engagement clamper,at each opposite side with respect to the column the engagement clamper is raised from the inner surface of the male fastener such that an opening is provided corresponding to the engagement clamper. The female fastener is provided with a central portion at a center thereof for connecting with the male fastener, the central portion has a wall and defines a guiding hole for receiving the column, and a respective side arm extending from the wall of the central portion is provided to enter the opening of the male fastener for complete engagement with the engagement clamper. The engagement is formed by the male fastener and the female fastener being stacked to each other and connected, making the male fastener rotate clockwise, making the side arm enters the opening of engagement clamper.

Abstract: An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders an to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digital terminal (RDT) with analog, T1 or SONET feeders and any conventional link medium. Data are put in DS1 format and multiplexed onto token ring optical loops for delivery to banks of channel units wherein the optical signals are translated to electrical signals for delivery to the Cus and subscribers. A method and apparatus is provided for mapping and demapping signals between virtual tributaries (VT) and digital signal formats in the RDT of an integrated digital loop carrier.

Abstract: Methods and apparatuses are discussed for generating a temperature compensated signal, used for example to provide a signal with a delay within a pre-specified range over a range of temperatures to a sense amplifier of a memory array. In response to a start signal, a varying signal is generated. A clock signal causes additional loads of impedance to be coupled to the varying signal, for example via control circuitry generating temperature compensating signals.

Abstract: An integrated circuit has a circuit for adjusting the time period of an output signal. The adjustment can compensate for semiconductor processing variations varying from wafer to wafer. The circuit adjusts the delay generated by an adjustable delay line, and adjusts the occurrence in time of the trailing edge of the output signal. A value which corresponds with a suitable delay to be generated by the adjustable delay line is stored in nonvolatile storage on the integrated circuit.

Abstract: A method is provided of regulating a supply voltage for providing a bit line voltage in a semiconductor memory device where the bit line voltage is provided to memory cells in a bit line from the supply voltage through a bit switch. A bit line current provided to the memory cells is detected. The supply voltage is adjusted responsive to the deducted bit line current to at least partially compensate for a voltage drop across the bit switch where the voltage drop is dependent at least in part on the bit line current.

Abstract: A method of overerase correction for memory cells in a memory array after the memory cells have been erased is provided comprising the following steps: (a) setting a gate voltage of memory cells from a first selected bit line exhibiting leakage current above a threshold value to an initial voltage level; (b) applying a series of overerase correction pulses to the first selected bit line during a selected time period; (c) detecting during the selected time period whether the bit line exhibits leakage current above the threshold value; (d) if the bit line exhibits leakage current above the threshold value after the selected time period, increasing the gate voltage and repeating steps (b) and (c); and (e) if it is detected that the bit line does not exhibit leakage current above the threshold value during the selected time period, selecting a second bit line and repeating steps (a) through (d).

Abstract: An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders an to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digital terminal (RDT) with analog, T1 or SONET feeders and any conventional link medium. Data are put in DS1 format and multiplexed onto token ring optical loops for delivery to banks of channel units wherein the optical signals are translated to electrical signals for delivery to the Cus and subscribers. A method and apparatus is provided for mapping and demapping signals between virtual tributaries (VT) and digital signal formats in the RDT of an integrated digital loop carrier.

Abstract: An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders and to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digital terminal (RDT) with analog, T1 or SONET feeders and any conventional link medium. Data are put in DS1 format and multiplexed onto token ring optical loops for delivery to banks of channel units wherein the optical signals are translated to electrical signals for delivery to the CUs and subscribers. A method and apparatus is provided for mapping and demapping signals between virtual tributaries (VT) and digital signal formats in the RDT of an integrated digital loop carrier.

Abstract: An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders and to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digital terminal (RDT) with analog, T1 or SONET feeders and any conventional link medium. Data are put in DS1 format and multiplexed onto token ring optical loops for delivery to banks of channel units wherein the optical signals are translated to electrical signals for delivery to the CUs and subscribers. A method and apparatus is provided for mapping and demapping signals between virtual tributaries (VT) and digital signal formats in the RDT of an integrated digital loop carrier.