Abstract: A multi-path initialization system includes a chassis. At least one storage device is housed in the chassis and includes an initialization path database storing respective initialization path information for each of a plurality of different initialization paths, and an initialization firmware volume database storing a plurality of initialization firmware volumes. An initialization subsystem is housed in the chassis, is coupled to the storage device(s), and receives an initialization path instruction to perform an initialization process according to an initialization path. The initialization subsystem identifies initialization path information for the initialization path that is included in the plurality of different initialization paths in the initialization path database, and identifies a subset of the plurality of initialization firmware volumes in the initialization firmware volume database based on the initialization path information.

Abstract: A coater cup deformation testing device includes a supporting board, a first plate and a second plate. The first plate is located on a first side surface of the supporting board. The first plate is circular and has a first diameter. The second plate is located on the first plate or on a second side surface of the supporting board. The second side surface is opposite to the first side surface. The second plate is circular and has a second diameter less than the first diameter. An area of each of the first and second plates is less than an area of the supporting board. A projection of each of the first and second plates on the supporting board is formed within the supporting board.

Abstract: A display panel including a substrate, scan lines, data lines, pixel structures, and a light shielding pattern layer is provided. The substrate is provided with a display area. The scan lines and the data lines are disposed on the substrate, and intersect with each other. The pixel structures are disposed in the display area, and each includes a display transistor and a pixel electrode. The display transistor includes a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is disposed between the substrate and the first semiconductor pattern, and is electrically connected to one of the scan lines. The first source electrode is electrically connected to one of the data lines. The pixel electrode is electrically connected to the first drain electrode of the display transistor. The light shielding pattern layer is disposed between the first gate electrode and the substrate, and has a first opening overlapping the first gate electrode.

Abstract: A semiconductor structure includes a substrate, a conductive region, a first insulation layer, a second insulation layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The low-k spacer is formed between a sidewall of the gate structure and the first insulation layer. The gate contact is landed on a top surface of the gate structure. A proximity distance between a sidewall of the gate contact and the conductive region contact along a top surface of the second insulation layer is in a range of from about 4 nm to about 7 nm. A method for manufacturing a semiconductor structure is also provided.

Abstract: A female-side connector assembly and its female-side connector and male-side connector, wherein the provided female-side connector and male-side connector are equipped with a metal shell and an insulating base. The metal shell can mate with the insulating base to form a locking side wall, allowing the male-side connector to lock the female-side connector through the locking side wall, preventing the male-side connector from disengaging from the locked female-side connector. This addresses the technical issues of the male-side connector easily disengaging from the locked female-side connector, ensuring that the signal transmission functionality between the female-side connector and the male-side connector meets expectations, thereby enabling the connector assembly to be widely applied in various electronic devices.

Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a fin isolation structure formed beside the nanostructures. The structure also includes a work function layer surrounding the nanostructures and covering a sidewall of the fin isolation structure. The structure also includes a gate electrode layer covering the work function layer. The gate electrode layer has an extending portion surrounded by the work function layer.

Abstract: A system and method for chemical mechanical polishing (“CMP”) pad replacement on a CMP processing tool. A platen carrier having two or more platens is positioned within a platen cleaning process module. Each platen includes a CMP pad affixed thereto, and is capable of being independently rotated during operations. When a pad requires replacement, the platen carrier rotates towards a pad tearer tool, which extends and pivots to remove the used pad from the platen as the carrier rotates. A pad tape replacement module is positioned above the CMP tool with pad tape extending from a supply roll to a recycle roll. As the pad tape transits through the module, a backing of the tape is separated and recycled. A pad disposed in the pad tape is then applied to a platen via a pressure roller.

Abstract: One or more embodiments of the disclosure are directed to methods of forming structures that are useful for FEOL and BEOL processes. Embodiments of the present disclosure advantageously provide methods of depositing a gapfill material, such as titanium nitride (TiN), in high aspect ratio (AR) structures with small dimensions. Some embodiments advantageously provide seam-free high-quality TiN films to fill high AR trenches with small dimensions. Embodiments of the present disclosure advantageously provide methods of filling 3D structures, such as FinFETs, GAAs, and the like, with a gapfill material without creating a seam. One or more embodiments include selective deposition processes using a carbon (C) layer in order to provide seam-free TiN gapfill in 3D structures, such as GAA devices.

Abstract: An antenna device based on a transparent substrate and a method of configuring an antenna device are provided. The antenna device includes a transparent substrate, a first dielectric layer, and an antenna. The transparent substrate includes a first surface and a second surface opposite to the first surface. The first dielectric layer includes a third surface and a fourth surface opposite to the third surface, wherein the first dielectric layer is in contact with the first surface via the third surface to be disposed on the transparent substrate, wherein a permittivity of the first dielectric layer is less than a permittivity of the transparent substrate. The antenna includes a radiation part, wherein the radiation part is disposed on one of the second surface and the fourth surface.

Abstract: A three-terminal power line fault location and correction system and method, and a computer readable storage medium. An electronic device is electrically connected with a plurality of terminal devices. When a fault occurs at a certain position of the power line, each terminal device detects the fault to generate a fault distance corresponding to the fault. The electronic device corrects the fault distance as follows: the corrected fault distance of one of the terminal devices=(an actual distance between the terminal device and a divergence point+a function of actual distances between the other two terminal devices and the divergence point)*the fault distance corresponding to the terminal device/(the fault distance corresponding to the terminal device+the fault distance corresponding to a function of the actual distances between the other two terminal devices and the divergence point).

Abstract: A heat dissipation assembly is disclosed and includes a frame and a fan. The frame includes a heat conduction channel and an airflow intake. The heat conduction channel is communication with an exterior through airflow intake. The frame includes a first plane, a second plane and an inclined plane. The first plane is disposed adjacent to the airflow intake. The inclined plane is connected between the first plane and the second plane. The second plane includes an inlet. The heat conduction channel is in communication between the airflow intake and the inlet. A cross-section area of the heat conduction channel adjacent to the airflow intake is greater than that of the heat conduction channel adjacent to the inlet. The fan is spatially corresponding to the inlet, and assembled with the frame to form an outlet in communication with the airflow intake and the heat conduction channel through the inlet.

Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.

Abstract: A calibration method for emulating a Group III-V semiconductor device, a method for determining trap location within a Group III-V semiconductor device and method for manufacturing a Group III-V semiconductor device are provided. Actual tape-out is performed according to an actual process flow of the Group III-V semiconductor device for manufacturing the Group III-V semiconductor devices and PCM Group III-V semiconductor device. Actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are obtained and the actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are compared to determine locations where one or more traps appear.

Abstract: A semiconductor device includes a bipolar junction transistor (BJT) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. The BJT structure includes active regions having different widths that form the emitters, the collectors, and the bases.

Abstract: Disclosed is a method for training a graphics processing neural network with a patch-based approach, which involves calculating an overlapping size and an invalid size of an output of each of at least one of multiple feature extraction layers of the graphic processing neural network according to a predetermined cropping scheme, dividing an input image into first patches in the forward pass and the first gradients into second patches in the backward pass to run streamline operation of the first and second patches. Before training, each first patch overlaps neighboring first patches at adjacent edges. In the forward pass, an invalid portion of the output of each of the at least one of the feature extraction layers cropped out based on the predetermined cropping scheme and a corresponding invalid size. Such method secures streamline operation in favor of enhanced memory utilization in training and accurate model prediction.

Abstract: A method of displaying a rear-view image and a digital dashboard using the method are provided. The method includes: receiving a rear-view image; and displaying the rear-view image on a default area of a display in response to receiving a signal associated with a direction indicator light, wherein the default area corresponds to the direction indicator light.

Abstract: Methods of manufacturing electronic devices, such as transistors (negative metal-oxide-semiconductor (NMOS) transistors (e.g., an N-metal stack) and positive metal-oxide-semiconductor (PMOS) transistors (e.g., a P-metal stack)) are described. Embodiments of the disclosure are directed to methods of improving PMOS transistor performance by inhibiting N-metal layer growth. The present disclosure provides two types of processes to reduce or inhibit N-metal layer growth. The disclosure provides methods which include forming a self-assembled monolayer (SAM) on the metal surface (e.g., titanium nitride (TiN)) of the PMOS, and methods which include forming a silicon-containing layer such as silicon oxide (SiOx) on the TiN surface. These two types of processes significantly reduce or inhibit the subsequent growth of an N-metal layer, such as titanium aluminum carbide (TiAlC), on the TiN surface of the PMOS.

Abstract: A solid-state drive (SSD) controller is operable to determine whether M supply voltage(s) supplied to a NAND flash memory is correct. The SSD controller includes: a voltage detector configured to receive the M supply voltage(s) and thereby generate a detection result, wherein the M is a positive integer; a voltage inquiry module configured to output an inquiry signal to the NAND flash memory and thereby receive a response signal from the NAND flash memory, and configured to generate an inquiry result according to the response signal, wherein the inquiry result indicates M specified supply voltage(s) applicable to the NAND flash memory; and a voltage decision module configured to receive the detection result and the inquiry result, and configured to determine whether the M supply voltage(s) is/are equivalent to the M specified voltage(s) according to the detection result and the inquiry result and thereby generate a decision result.

Abstract: Embodiments disclosed herein describe methods of forming semiconductor devices. The methods may include etching vias and trenches in a middle-of-line (MOL) layer that has a low-k dielectric layer, a sacrificial nitride layer, and a hard mask layer. The methods may also include depositing a thin nitride layer within the via trench, depositing a carbon layer on the thin nitride layer within the vias and trenches, etching back the thin nitride layer to expose a portion of the hard mask layer, removing the hard mask layer and the carbon layer, and removing the thin nitride layer and the sacrificial nitride layer.

Abstract: A display panel includes a substrate, multiple scan lines, multiple data lines, and multiple pixel structures. The scan lines and the data lines are disposed on the substrate. The pixel structure is disposed on the substrate and electrically connected to the scan lines and the data lines, and includes an active device, a pixel electrode, a capacitor electrode, an overcoat layer, a first common electrode, a second common electrode, a first passivation layer, and a second passivation layer. The active device is electrically connected one scan line, one data line, and the pixel electrode. The capacitor electrode extends from a drain and is electrically connected to the pixel electrode. The overcoat layer is disposed between the pixel electrode and the capacitor electrode. The first common electrode overlaps the capacitor electrode, and is located between the overcoat layer and the capacitor electrode.