Abstract: A multi-radar based detection device and detection method for a target object are provided. In the detection method, a first detection result corresponding to a first detection space and a second detection result corresponding to a second detection space are received. The first detection space entering a first status is determined in response to the first detection result indicating that the target object in the first detection space moves to an overlapping area between the first detection space and the second detection space. First information is output in response to determining that the first detection space enters the first status. The second detection space entering a second status is determined in response to the second detection result indicating that the target object not in the second detection space appears in the overlapping area. Second information is output in response to determining that the second detection space enters the second status.

Abstract: In a method of pattern formation information including a pattern size on a reticle is received. A width of an EUV radiation beam is adjusted in accordance with the information. The EUV radiation beam is scanned on the reticle. A photo resist layer is exposed with a reflected EUV radiation beam from the reticle. An increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width is greater when the width before adjustment is W1 compared to an increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width when the width before adjustment is W2 when W1>W2.

Abstract: A system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.

Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.

Abstract: An optical structure is provided. The optical structure includes a substrate, a light-emitting element, a glue layer, and a light-adjusting element. The light-emitting element is disposed on the substrate. The glue layer covers the light-emitting element. The light-adjusting element is disposed on the glue layer. Moreover, the refractive index of the glue layer is different from the refractive index of the light-adjusting element.

Abstract: Methods, computer systems, and apparatus, including computer programs encoded on computer storage media, for training an audio-processing neural network that includes at least (1) a first encoder network having a first set of encoder network parameters and (2) a decoder network having a set of decoder network parameters. The system obtains a set of un-labeled audio data segments, and generates, from the set of un-labeled audio data segments, a set of encoder training examples. The system performs training of a second encoder neural network that includes at least the first encoder neural network on the set of generated encoder training examples. The system also obtains one or more labeled training examples, and performs training of the audio-processing neural network on the labeled training examples.

Abstract: A method can include determining which computing units in a computing-in-memory (CIM) macro are to be turned off, the CIM macro including an array of the computing units with X rows and Y columns, the X rows of computing units being organized into N row-groups, each row-group including multiple rows of computing units, the Y columns of computing units being organized into M column-groups, each column-group including multiple columns of computing units, based on the determination of which computing units in the CIM macro are to be turned off, turning off at least one row-group or column-group of computing units, each row-group and column-group of computing units being separately controllable to be turned off, and performing a computation based on kernel weights and activations of a neural network stored in the active computing units in the CIM macro that are not turned off.

Abstract: The present disclosure provides a method of forming a semiconductor structure. The method includes providing a substrate including an isolation region, an active region adjacent to the isolation region, and a first top surface, wherein the isolation region includes an isolation trench filled with a dielectric material, and the active region includes a gate trench filled with a gate electrode material; forming a hard mask on the substrate; and performing an etching process to partially remove portions of the dielectric material and gate electrode material exposed by the hard mask to form a second top surface of the dielectric material and a third top surface of the gate electrode material, wherein the second top surface and the third top surface are substantially at the same level and are substantially lower than the first top surface.

Abstract: A target droplet source for an extreme ultraviolet (EUV) source includes a droplet generator configured to generate target droplets of a given material. The droplet generator includes a nozzle configured to supply the target droplets in a space enclosed by a chamber. The target droplet source further includes a sleeve disposed in the chamber distal to the nozzle. The sleeve is configured to provide a path for the target droplets in the chamber.

Abstract: A backlight module has a reflective sheet and a light board. The reflective sheet has a body and two side walls located on two sides of the body and being opposite to each other. Each side wall has a tab. A storage space of the reflective sheet is formed between said tabs on the two side walls, the two side walls, and a bottom of the body. Each side of the light board has a recess portion recessed thereon for corresponding to the tab on the side wall of the reflective sheet. The light board is located in the storage space and limited on the reflective sheet by the tab. A display has the aforementioned backlight module and a display panel. The display panel is connected with the backlight module, and the light board faces toward the display panel.

Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.

Abstract: A method of operating a memory circuit includes generating, by a first memory cell array, a first current in response to a first voltage, generating, by a tracking circuit, a second set of leakage currents, generating, by a first current source, a second write current, and mirroring, by a first current mirror. The first current includes a first set of leakage currents and a first write current. The first current is in a first path with a second current in a second path. The second current includes the second set of leakage currents and the second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents. The second set of leakage currents is configured to track the first set of leakage currents of the first memory cell array.

Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

Abstract: The present disclosure provides a method of forming a semiconductor structure. The method comprises providing a substrate comprising an isolation region, an active region adjacent to the isolation region, and a first top surface, wherein the isolation region includes an isolation trench filled with a dielectric material, and the active region includes a gate trench filled with a gate electrode material; forming a hard mask on the substrate; and performing an etching process to partially remove portions of the dielectric material and gate electrode material exposed by the hard mask to form a second top surface of the dielectric material and a third top surface of the gate electrode material, wherein the second top surface and the third top surface are substantially at the same level and are substantially lower than the first top surface.

Abstract: A method for performing a lithography process is provided. The method includes forming a photoresist layer over a substrate, providing a plurality of target droplets to a source vessel, and providing a plurality of first laser pulses according to a control signal provided by a controller to irradiate the target droplets in the source vessel to generate plasma as an EUV radiation. The plasma is generated when the control signal indicates a temperature of the source vessel is within a temperature threshold value. The method further includes directing the EUV radiation from the source vessel to the photoresist layer to form a patterned photoresist layer and developing and etching the patterned photoresist layer to form a circuit layout.

Abstract: A memory circuit includes a first driver circuit, a memory cell array including a first column of memory cells, a first transistor coupled between the first driver circuit and the memory cell array, a second driver circuit, a first column of tracking cells and a header circuit coupled to the first driver circuit and the second driver circuit. The first transistor is configured to receive a first select signal. The first column of tracking cells is configured to track a leakage current of the first column of memory cells, and is coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.

Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.

Abstract: A method of maximizing power efficiency for a power amplifier system comprises obtaining a power supply voltage; determining a first voltage level sufficient for a power amplifier of the power amplifier system to output an output power; determining a second voltage level lower than the first voltage level; determining whether the power amplifier is activated, to generate a determination result; determining to convert the power supply voltage into a supply voltage with the first voltage level or the second voltage level according to the determination result; and supplying the power amplifier with the supply voltage.

Abstract: Semiconductor devices and methods of manufacture are provided whereby fences are formed over a substrate and III-V materials are grown over the substrate, wherein the fences block growth of the III-V materials. As such, smaller areas of the III-V materials are grown, thereby preventing stresses that occur with the growth of larger sheets.