Patents by Inventor Chung-Cheng Chou

Chung-Cheng Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220254412
    Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.
    Type: Application
    Filed: September 9, 2021
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Jun Lin, Chin-I Su, Pei-Ling Tseng, Chung-Cheng Chou
  • Publication number: 20220238155
    Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
    Type: Application
    Filed: April 15, 2022
    Publication date: July 28, 2022
    Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih
  • Patent number: 11393512
    Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih
  • Patent number: 11393528
    Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first transistor configured to generate a voltage difference based on a first current and an activation voltage, and is configured to output the activation voltage and a bias voltage based on the voltage difference. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to receive the activation voltage and conduct a second current responsive to the drive voltage and the activation voltage.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Cheng Chou, Chien-An Lai, Hsu-Shun Chen, Zheng-Jun Lin, Pei-Ling Tseng
  • Patent number: 11373947
    Abstract: An interconnect structure includes an interconnect structure includes an etching stop layer; a dielectric layer and an insert layer on the etching stop layer, and a conductive feature in the dielectric layer, the insert layer and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
  • Patent number: 11348638
    Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Pei-Ling Tseng
  • Patent number: 11336174
    Abstract: A system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Cheng Chou, Tien-Yen Wang
  • Patent number: 11309022
    Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 19, 2022
    Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih
  • Publication number: 20210407594
    Abstract: A memory circuit includes a first driver circuit, a first column of memory cells coupled to the first driver circuit, a first current source, a tracking circuit configured to track a leakage current of the first column of memory cells, and a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.
    Type: Application
    Filed: November 24, 2020
    Publication date: December 30, 2021
    Inventors: Chin-I SU, Chung-Cheng CHOU, Yu-Der CHIH, Zheng-Jun LIN
  • Patent number: 11181421
    Abstract: A spectrometer is disclosed. The spectrometer includes a fiber input, a collimator lens, a rotating shaft, a grating, a focal lens and a focal plane which have arranged in order. A broadband incident light of the fiber input becomes a first parallel beam through the collimator lens and separated by the grating into multiple parallel beams of different wavelengths and then focused by the focal lens to emit an output beams to an imaging position on the focal plane. The spectrometer can rotate the collimator lens and fiber input to change the imaging position on the focal plane.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: November 23, 2021
    Assignee: Crystalvue Medical Corporation
    Inventors: William Wang, Che-Liang Tsai, Chung-Cheng Chou
  • Publication number: 20210280245
    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 9, 2021
    Inventors: Yu-Der CHIH, Chung-Cheng CHOU, Wen-Ting CHU
  • Publication number: 20210249075
    Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 12, 2021
    Inventors: Chung-Cheng Chou, Tien-Yen Wang
  • Publication number: 20210241830
    Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.
    Type: Application
    Filed: November 30, 2020
    Publication date: August 5, 2021
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Pei-Ling Tseng
  • Publication number: 20210201994
    Abstract: A method of forming a filament in a resistive random-access memory (RRAM) device includes applying a cell voltage across a resistive layer of the RRAM device, detecting an increase in a current through the resistive layer generated in response to the applied cell voltage, and in response to detecting the increase in the current, using a first switching device to reduce the current through the resistive layer.
    Type: Application
    Filed: March 12, 2021
    Publication date: July 1, 2021
    Inventors: Chung-Cheng CHOU, Zheng-Jun LIN, Pei-Ling TSENG
  • Publication number: 20210174871
    Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first transistor configured to generate a voltage difference based on a first current and an activation voltage, and is configured to output the activation voltage and a bias voltage based on the voltage difference. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to receive the activation voltage and conduct a second current responsive to the drive voltage and the activation voltage.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 10, 2021
    Inventors: Chung-Cheng CHOU, Chien-An LAI, Hsu-Shun CHEN, Zheng-Jun LIN, Pei-Ling TSENG
  • Patent number: 11024381
    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Wen-Ting Chu
  • Publication number: 20210151086
    Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.
    Type: Application
    Filed: October 2, 2020
    Publication date: May 20, 2021
    Inventors: CHIEN-AN LAI, CHUNG-CHENG CHOU, YU-DER CHIH
  • Patent number: 10991426
    Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Cheng Chou, Tien-Yen Wang
  • Publication number: 20210119531
    Abstract: A system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Inventors: Chung-Cheng Chou, Tien-Yen Wang
  • Publication number: 20210118499
    Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih