Abstract: Embodiments of the present disclosure relate to a method of forming a low-k dielectric material, for example, a low-k gate spacer layer in a FinFET device. The low-k dielectric material may be formed using a precursor having a general chemical structure comprising at least one carbon atom bonded between two silicon atoms. A target k-value of the dielectric material may be achieved by controlling carbon concentration in the dielectric material.

Abstract: Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming an interconnect structure over a substrate. The forming the interconnect structure over the semiconductor device structure includes forming a dielectric layer, then performing an annealing process, then forming one or more openings in the dielectric layer, then performing a first ultraviolet (UV) curing process, and then forming conductive features in the one or more openings.

Abstract: A structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and contacting the first conductive feature. An air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. A protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.

Abstract: An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.

Abstract: An integrated circuit structure includes a substrate, a transistor, a first dielectric layer, a metal contact, a first low-k dielectric layer, a second dielectric layer, and a first metal feature. The transistor is over the substrate. The first dielectric layer is over the transistor. The metal contact is in the first dielectric layer and electrically connected to the transistor. The first low-k dielectric layer is over the first dielectric layer. The second dielectric layer is over the first low-k dielectric layer and has a dielectric constant higher than a dielectric constant of the first low-k dielectric layer. The first metal feature extends through both second dielectric layer and the first low-k dielectric layer to the metal contact.

Abstract: An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.

Abstract: An integrated circuit structure includes a bulk semiconductor region, a first semiconductor strip over and connected to the bulk semiconductor region, and a dielectric layer including silicon oxide therein. Carbon atoms are doped in the silicon oxide. The dielectric layer includes a horizontal portion over and contacting a top surface of the bulk semiconductor region, and a vertical portion connected to an end of the horizontal portion. The vertical portion contacts a sidewall of a lower portion of the first semiconductor strip. A top portion of the first semiconductor strip protrudes higher than a top surface of the vertical portion to form a semiconductor fin. The horizontal portion and the vertical portion have a same thickness. A gate stack extends on a sidewall and a top surface of the semiconductor fin.

Abstract: A method includes forming a silicon layer on a wafer, forming an oxide layer in contact with the silicon layer, and, after the oxide layer is formed, annealing the wafer in an environment comprising ammonia (NH3) to form a dielectric barrier layer between, and in contact with, the silicon layer and the oxide layer. The dielectric barrier layer comprises silicon and nitrogen.

Abstract: An interconnect structure includes an interconnect structure includes an etching stop layer, a dielectric layer and an insert layer and a conductive line. The insert layer is located between the etching stop layer and the dielectric layer. The conductive line extends through the dielectric layer, the insert layer, and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.

Abstract: A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Abstract: An integrated circuit structure includes a bulk semiconductor region, a first semiconductor strip over and connected to the bulk semiconductor region, and a dielectric layer including silicon oxide therein. Carbon atoms are doped in the silicon oxide. The dielectric layer includes a horizontal portion over and contacting a top surface of the bulk semiconductor region, and a vertical portion connected to an end of the horizontal portion. The vertical portion contacts a sidewall of a lower portion of the first semiconductor strip. A top portion of the first semiconductor strip protrudes higher than a top surface of the vertical portion to form a semiconductor fin. The horizontal portion and the vertical portion have a same thickness. A gate stack extends on a sidewall and a top surface of the semiconductor fin.

Abstract: An interconnect structure includes an interconnect structure includes an etching stop layer; a dielectric layer and an insert layer on the etching stop layer, and a conductive feature in the dielectric layer, the insert layer and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.

Abstract: A method includes forming a silicon layer on a wafer, forming an oxide layer in contact with the silicon layer, and, after the oxide layer is formed, annealing the wafer in an environment comprising ammonia (NH3) to form a dielectric barrier layer between, and in contact with, the silicon layer and the oxide layer. The dielectric barrier layer comprises silicon and nitrogen.

Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.

Abstract: Semiconductor device structures comprising a spacer feature having multiple spacer layers are provided. In one example, a semiconductor device includes an active area on a substrate, the active area comprising a source/drain region, a gate structure over the active area, the source/drain region being proximate the gate structure, a spacer feature having a first portion along a sidewall of the gate structure and having a second portion along the source/drain region, wherein the first portion of the spacer feature comprises a bulk spacer layer along the sidewall of the gate structure, wherein the second portion of the spacer feature comprises the bulk spacer layer and a treated seal spacer layer, the treated seal spacer layer being disposed along the source/drain region and between the bulk spacer layer and the source/drain region, and a contact etching stop layer on the spacer feature.

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Abstract: A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia.

Abstract: A method includes etching a semiconductor substrate to form a trench, and depositing a dielectric layer using an Atomic Layer Deposition (ALD) cycle. The dielectric layer extends into the trench. The ALD cycle includes pulsing Hexachlorodisilane (HCD) to the semiconductor substrate, purging the HCD, pulsing triethylamine to the semiconductor substrate, and purging the triethylamine. An anneal process is then performed on the dielectric layer.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.