Patents by Inventor Chung-Chiang Min
Chung-Chiang Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10276584Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. In some embodiments, a semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.Type: GrantFiled: January 18, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Chiang Min, Tsung-Hsueh Yang, Chang-Ming Wu, Shih-Chang Liu
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Publication number: 20180351081Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.Type: ApplicationFiled: July 30, 2018Publication date: December 6, 2018Inventors: Fu-Ting SUNG, Chung-Chiang MIN, Yuan-Tai TSENG, Chern-Yow HSU, Shih-Chang LIU
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Publication number: 20180122820Abstract: Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a control gate over a substrate and forming a dielectric layer covering the control gate. The method further includes forming a conductive layer having a first portion and a second portion over the dielectric layer. In addition, the first portion of the conductive layer is separated from the control gate by the dielectric layer. The method further includes forming an oxide layer on a top surface of the first portion of the conductive layer and removing the second portion of the conductive layer to form a memory gate.Type: ApplicationFiled: December 27, 2017Publication date: May 3, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Ting SUNG, Chung-Chiang MIN, Wei-Hang HUANG, Shih-Chang LIU, Chia-Shiung TSAI
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Patent number: 9859295Abstract: Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a substrate and forming a dielectric layer over the word line cell. The method further includes forming a conductive layer over the dielectric layer and polishing the conductive layer until the dielectric layer is exposed. The method further includes forming an oxide layer on a top surface of the conductive layer and removing portions of the conductive layer not covered by the oxide layer to form a memory gate.Type: GrantFiled: February 6, 2017Date of Patent: January 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Ting Sung, Chung-Chiang Min, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 9799665Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a mask layer over a substrate. The method includes forming a first isolation structure and a second isolation structure passing through the mask layer and penetrating into the substrate. The method includes thinning the mask layer to expose a first portion of the first isolation structure and a second portion of the second isolation structure. The method includes partially removing the first portion, the second portion, the third portion, and the fourth portion. The method includes removing the thinned mask layer. The method includes forming a first gate over the substrate and between the first isolation structure and the second isolation structure. The method includes forming a dielectric layer over the first gate. The method includes forming a second gate over the dielectric layer and above the first gate.Type: GrantFiled: May 24, 2017Date of Patent: October 24, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chang-Ming Wu, Tsung-Hsueh Yang, Chung-Chiang Min, Shih-Chang Liu
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Patent number: 9786674Abstract: Provided is a method of forming a decoupling capacitor device and the device thereof. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.Type: GrantFiled: November 16, 2015Date of Patent: October 10, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Chiang Min, Chang-Ming Wu, Shih-Chang Liu, Yuan-Tai Tseng
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Publication number: 20170287915Abstract: A method of manufacturing a semiconductor device includes forming a source/drain region in a substrate. An interlevel dielectric layer is formed on the substrate. A conducting plug is formed in the interlevel dielectric layer. The conducting plug is electrically coupled to the source/drain region. A crown oxide is formed on the interlevel dielectric layer. A deep trench is formed in the crown oxide to expose a top wall and a sidewall of the conducting plug. A spacer is formed on the sidewall of the conducting plug. A metal-insulator-metal film is formed in the deep trench.Type: ApplicationFiled: June 14, 2017Publication date: October 5, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Hsueh YANG, Chung-Chiang MIN, Chang-Ming WU, Shih-Chang LIU
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Publication number: 20170256553Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a mask layer over a substrate. The method includes forming a first isolation structure and a second isolation structure passing through the mask layer and penetrating into the substrate. The method includes thinning the mask layer to expose a first portion of the first isolation structure and a second portion of the second isolation structure. The method includes partially removing the first portion, the second portion, the third portion, and the fourth portion. The method includes removing the thinned mask layer. The method includes forming a first gate over the substrate and between the first isolation structure and the second isolation structure. The method includes forming a dielectric layer over the first gate. The method includes forming a second gate over the dielectric layer and above the first gate.Type: ApplicationFiled: May 24, 2017Publication date: September 7, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Ming WU, Tsung-Hsueh YANG, Chung-Chiang MIN, Shih-Chang LIU
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Publication number: 20170222128Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.Type: ApplicationFiled: May 10, 2016Publication date: August 3, 2017Inventors: FU-TING SUNG, CHUNG-CHIANG MIN, YUAN-TAI TSENG, CHERN-YOW HSU, SHIH-CHANG LIU
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Patent number: 9711508Abstract: A capacitor structure includes a deep trench, a contact plug, a spacer and a metal-insulator-metal film. The deep trench extends into a crown oxide substrate, and the contact plug is disposed entirely below the crown oxide substrate. The spacer lines the deep trench, and the metal-insulator-metal film is disposed in the deep trench.Type: GrantFiled: February 26, 2015Date of Patent: July 18, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Hsueh Yang, Chung-Chiang Min, Chang-Ming Wu, Shih-Chang Liu
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Patent number: 9673204Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure also includes a first isolation structure partially embedded in the substrate. The first isolation structure has a first upper surface with a first recess. The semiconductor device structure further includes a second isolation structure partially embedded in the substrate. In addition, the semiconductor device structure includes a first gate over the substrate and between the first isolation structure and the second isolation structure. The first gate extends onto the first upper surface to cover the first recess. The semiconductor device structure includes a second gate over the first gate.Type: GrantFiled: December 29, 2014Date of Patent: June 6, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chang-Ming Wu, Tsung-Hsueh Yang, Chung-Chiang Min, Shih-Chang Liu
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Publication number: 20170148803Abstract: Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a substrate and forming a dielectric layer over the word line cell. The method further includes forming a conductive layer over the dielectric layer and polishing the conductive layer until the dielectric layer is exposed. The method further includes forming an oxide layer on a top surface of the conductive layer and removing portions of the conductive layer not covered by the oxide layer to form a memory gate.Type: ApplicationFiled: February 6, 2017Publication date: May 25, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Ting SUNG, Chung-Chiang MIN, Wei-Hang HUANG, Shih-Chang LIU, Chia-Shiung TSAI
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Publication number: 20170141120Abstract: Provided is a method of forming a decoupling capacitor device and the device thereof. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.Type: ApplicationFiled: November 16, 2015Publication date: May 18, 2017Inventors: Chung-Chiang Min, Chang-Ming Wu, Shih-Chang Liu, Yuan-Tai Tseng
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Publication number: 20170125434Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. In some embodiments, a semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.Type: ApplicationFiled: January 18, 2017Publication date: May 4, 2017Inventors: Chung-Chiang Min, Tsung-Hsueh Yang, Chang-Ming Wu, Shih-Chang Liu
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Patent number: 9570457Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.Type: GrantFiled: August 26, 2014Date of Patent: February 14, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Chiang Min, Tsung-Hsueh Yang, Chang-Ming Wu, Shih-Chang Liu
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Patent number: 9564448Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device structure further includes a memory gate formed over the substrate and a first spacer formed on a sidewall of the memory gate. The semiconductor device structure further includes a contact formed over the memory gate, wherein a portion of the contact extends into the first spacer.Type: GrantFiled: May 21, 2015Date of Patent: February 7, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Ting Sung, Chung-Chiang Min, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 9536969Abstract: The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has cuboid shaped memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have planar upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced.Type: GrantFiled: September 23, 2014Date of Patent: January 3, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Hsueh Yang, Chung-Chiang Min, Chang-Ming Wu, Shih-Chang Liu
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Publication number: 20160254266Abstract: A capacitor structure includes a deep trench, a contact plug, a spacer and a metal-insulator-metal film. The deep trench extends into a crown oxide substrate, and the contact plug is disposed entirely below the crown oxide substrate. The spacer lines the deep trench, and the metal-insulator-metal film is disposed in the deep trench.Type: ApplicationFiled: February 26, 2015Publication date: September 1, 2016Inventors: Tsung-Hsueh YANG, Chung-Chiang MIN, Chang-Ming WU, Shih-Chang LIU
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Publication number: 20160190268Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure also includes a first isolation structure partially embedded in the substrate. The first isolation structure has a first upper surface with a first recess. The semiconductor device structure further includes a second isolation structure partially embedded in the substrate. In addition, the semiconductor device structure includes a first gate over the substrate and between the first isolation structure and the second isolation structure. The first gate extends onto the first upper surface to cover the first recess. The semiconductor device structure includes a second gate over the first gate.Type: ApplicationFiled: December 29, 2014Publication date: June 30, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Ming WU, Tsung-Hsueh YANG, Chung-Chiang MIN, Shih-Chang LIU
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Publication number: 20160086965Abstract: The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has cuboid shaped memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have planar upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced.Type: ApplicationFiled: September 23, 2014Publication date: March 24, 2016Inventors: Tsung-Hsueh Yang, Chung-Chiang Min, Chang-Ming Wu, Shih-Chang Liu