Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device structure further includes a memory gate formed over the substrate and a first spacer formed on a sidewall of the memory gate. The semiconductor device structure further includes a contact formed over the memory gate, wherein a portion of the contact extends into the first spacer.

Abstract: Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device further includes a memory gate disposed over the substrate and adjacent to the word line cell and a spacer on a sidewall of the memory gate. The spacer and the word line cell are at opposite sides of the memory gate. In addition, an angle between a top surface of the memory gate and a sidewall of the memory gate is in a range from about 75° to about 90°.

Abstract: Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device further includes a memory gate disposed over the substrate and adjacent to the word line cell and a spacer on a sidewall of the memory gate. The spacer and the word line cell are at opposite sides of the memory gate. In addition, an angle between a top surface of the memory gate and a sidewall of the memory gate is in a range from about 75° to about 90°.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate structures having asymmetric sidewalls including a tall side and a short side. Adjacent ones of the plurality of gate structures are separated by a tall side-tall side region and a short side-short side region. The method further comprises forming a spacer layer over the plurality of gate structures and a bottom surface of the tall side-tall side region and the short side-short side region, depositing an oxide layer over the spacer layer, etching the bottom surface portions of the oxide layer, and selectively etching the sidewall portions of the oxide layer in the tall side-tall side region.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate structures having asymmetric sidewalls including a tall side and a short side. Adjacent ones of the plurality of gate structures are separated by a tall side-tall side region and a short side-short side region. The method further comprises forming a spacer layer over the plurality of gate structures and a bottom surface of the tall side-tall side region and the short side-short side region, depositing an oxide layer over the spacer layer, etching the bottom surface portions of the oxide layer, and selectively etching the sidewall portions of the oxide layer in the tall side-tall side region.

Abstract: A method for forming a deep trench includes providing a substrate with a bottom layer and a top layer; performing a first etching process to etch the top layer, the bottom layer and the substrate so as to form a recess; selectively depositing a liner covering the top layer, the bottom layer and part of the substrate in the recess; using the liner as an etching mask to perform a second dry etching to etch the recess unmasked by the liner so as to form a deep trench; performing a selective wet etching to remove the top layer; and performing a post wet etching to enlarge the deep trench.

Abstract: A method of manufacturing a supporting structure for a stack capacitor in a semiconductor device is provided. The method includes the following steps. The first step is providing a multi-layer structure including an etching stop layer, a silicon oxide layer and a silicon nitride layer. The second step is etching the silicon nitride layer and the silicon oxide layer to form a plurality of filling recesses in the silicon oxide layer, in which each the filling recess has a lateral surface and a bottom surface. The third step is forming a protecting layer at each the lateral surface. The fourth step is etching the silicon oxide layer to expose the etching stop layer. The fifth step is removing the protecting layer on the each lateral surface, thereby forming the supporting structure.

Abstract: A method for forming a deep trench includes providing a substrate with a bottom layer and a top layer; performing a first etching process to etch the top layer, the bottom layer and the substrate so as to form a recess; selectively depositing a liner covering the top layer, the bottom layer and part of the substrate in the recess; using the liner as an etching mask to perform a second dry etching to etch the recess unmasked by the liner so as to form a deep trench; performing a selective wet etching to remove the top layer; and performing a post wet etching to enlarge the deep trench.