Patents by Inventor Chung-Chiang WU
Chung-Chiang WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12272556Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.Type: GrantFiled: June 29, 2022Date of Patent: April 8, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Shiung Tsai, Chung-Chiang Wu, Wei-Fan Liao, Han-Ti Hsiaw
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Patent number: 12255104Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.Type: GrantFiled: August 2, 2023Date of Patent: March 18, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
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Patent number: 12183629Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.Type: GrantFiled: July 20, 2022Date of Patent: December 31, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Pin-Hsuan Yeh, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
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Patent number: 12183638Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.Type: GrantFiled: November 1, 2023Date of Patent: December 31, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Han Tsai, Chung-Chiang Wu, Cheng-Lung Hung, Weng Chang, Chi On Chui
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Publication number: 20240387257Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Pin-Hsuan Yeh, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
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Publication number: 20240387679Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Chia-Ching Lee, Hung-Chin Chung, Chung-Chiang Wu, Hsuan-Yu Tung, Kuan-Chang Chiu, Chien-Hao Chen, Chi On Chui
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Publication number: 20240387276Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su
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Patent number: 12148810Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.Type: GrantFiled: January 13, 2023Date of Patent: November 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Jo-Chun Hung, Wei-Cheng Wang, Kuan-Ting Liu, Chi On Chui
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Publication number: 20240379810Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Jo-Chun Hung, Wei-Cheng Wang, Kuan-Ting Liu, Chi On Chui
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Publication number: 20240379448Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: Hsin-Han Tsai, Chung-Chiang Wu, Cheng-Lung Hung, Weng Chang, Chi On Chui
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Patent number: 12142530Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.Type: GrantFiled: July 1, 2021Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su
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Patent number: 12142531Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.Type: GrantFiled: May 2, 2022Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yen Tsai, Chung-Chiang Wu, Tai-Wei Hwang, Hung-Chin Chung, Wei-Chin Lee, Da-Yuan Lee, Ching-Hwanq Su, Yin-Chuan Chuang, Kuan-Ting Liu
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Publication number: 20240363424Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.Type: ApplicationFiled: July 11, 2024Publication date: October 31, 2024Inventors: Chung-Chiang Wu, Hsin-Han Tsai, Wei-Chin Lee, Chia-Ching Lee, Hung-Chin Chung, Cheng-Lung Hung, Da-Yuan Lee
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Publication number: 20240363627Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.Type: ApplicationFiled: July 9, 2024Publication date: October 31, 2024Inventors: Kuan-Chang Chiu, Chia-Ching Lee, Chien-Hao Chen, Hung-Chin Chung, Hsien-Ming Lee, Chi On Chui, Hsuan-Yu Tung, Chung-Chiang Wu
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Publication number: 20240304725Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.Type: ApplicationFiled: May 21, 2024Publication date: September 12, 2024Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su
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Patent number: 12087767Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.Type: GrantFiled: December 20, 2022Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Chang Chiu, Chia-Ching Lee, Chien-Hao Chen, Hung-Chin Chung, Hsien-Ming Lee, Chi On Chui, Hsuan-Yu Tung, Chung-Chiang Wu
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Patent number: 12087637Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.Type: GrantFiled: December 14, 2020Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Chiang Wu, Hsin-Han Tsai, Wei-Chin Lee, Chia-Ching Lee, Hung-Chin Chung, Cheng-Lung Hung, Da-Yuan Lee
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Patent number: 12040235Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.Type: GrantFiled: July 21, 2022Date of Patent: July 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
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Patent number: 12033893Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.Type: GrantFiled: July 26, 2023Date of Patent: July 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Chiang Wu, Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su
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Publication number: 20240222108Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.Type: ApplicationFiled: March 18, 2024Publication date: July 4, 2024Inventors: Chia-Ching Lee, Chung-Chiang Wu, Shih-Hang Chiu, Hsuan-Yu Tung, Da-Yuan Lee