Abstract: A fault detection method comprises the following steps. Receiving a first original sequence comprising a plurality of first data. Receiving a second original sequence comprising a plurality of second data. Aligning the first original sequence with the second original sequence according to trends of value changing of the first data and the second data. Performing an average operation on the aligned first original sequence and second original sequence to establish a standard sequence. Performing a difference operation between the first original sequence and the standard sequence to obtain a first total difference value. Performing a difference operation between the second original sequence and the standard sequence to obtain a second total difference value. When the first total difference value and/or the second total difference value is greater than an upper limit value, determining that the first original sequence and/or the second total difference value is abnormal.

Abstract: A non-transitory computer readable storage medium storing a data structure and a computer program includes: a number of stored files each of which includes a number of fields including: at least one first field and at least one second field. Said at least one first field stores tag data of a region of interest of a video file, and said at least one second field stores inference data associated with the region of interest of a video file. The computer program reads the stored files and outputs a field content of the fields of the stored files when executed by a data processing device. The present disclosure also provides an artificial intelligence inference method and system configured to perform: searching the data structure according to a query to obtain a field content, and performing analysis according to input data and the field content.

Abstract: The present application provides a synchronous rectification circuit and a control method thereof. A switching element of the synchronous rectification circuit is controlled to turn on or turn off by detecting the occurrence of a positive or negative transition of the inductive voltage of the secondary winding. The synchronous rectification circuit comprises a transition detector for coupling to the secondary winding, a transition controller for coupling to the transition detector, and a switching element comprising a control terminal for coupling to the transition controller.

Abstract: The present application provides a synchronous rectification circuit, which adopts a multiplexer that selectively inputs a first reference signal or a second reference signal to a comparator by coupling the first and second reference signal. A comparing signal is generated to a switch element by comparing a switch input signal. Hereby, the switch element is under control for synchronous rectification.

Abstract: A query-oriented event recognition system includes a capturing unit, an analyzing inference engine assembly, a synchronization processing unit and an event definition unit. The capturing unit is configured to capture at least one data flow including a plurality of time points and data, and each time points is corresponding to a data. The analysis and inference engine assembly includes a plurality of inference engines. The analysis and inference engine assembly is configured to analyze and reason the data of the time points by the inference engines to generate at least one inference data corresponding to the data at each time point. The synchronization processing unit is configured to generate an inference data set corresponding to each time point according to the data flow and the inference data. The event definition unit is configured to find an event query result matching up with the inference data set through a query statement.

Abstract: A low supply noise comparison circuit include a first dynamic comparator, a second dynamic comparator and a control circuit. The first dynamic comparator is a pre-amplifier for the second dynamic comparator. The control circuit will activate the second dynamic comparator after the first dynamic comparator is activated for a preset time. So the first and second dynamic comparators will not be activated at the same time and a high supply noise is avoided.

Abstract: A comparator circuit with low power consumption and low kickback noise includes a first dynamic comparator and a second dynamic comparator. The first dynamic comparator is a pre-amplifier for the second dynamic comparator. An enable switch which is connected to the first dynamic comparator has a control terminal connected to a resistance device. The resistance device and the enable switch form a RC delay circuit to reduce the kickback noise of the comparator circuit. Since the comparator circuit is composed of dynamic comparators, the power consumption of the comparator circuit is lower.

Abstract: A cochlear implant device comprises a receiver, a processing device, a first electrode and a second electrode. The receiver is configured to receive outside voice signal. The processing device is coupled to the receiver, configured to receive and transfer the voice signal to an electrical stimulation signal. The first electrode connects to the processing device, disposed on stapes footplate ligament or oval window. The second electrode connects to the processing device, disposed on round window. Wherein the electrical stimulation signal is applied to stapes footplate ligament, oval window or round window to stimulate acoustic nerve through the first electrode or the second electrode.

Abstract: A pseudo resistor with tunable resistance including a first transistor and a second transistor is provided. The first transistor has a first terminal, a second terminal and a control terminal. The first terminal of the first transistor serves as a first terminal of the pseudo resistor. The control terminal of the first transistor receives a control voltage. The first transistor is controlled by the control voltage, such that the first transistor operates in a weak inversion region. The second transistor has a first terminal, a second terminal and a control terminal. The first terminal of the second transistor is coupled to the second terminal of the first transistor. The second terminal of the second transistor and the control terminal of the second transistor are coupled to each other to serve as a second terminal of the pseudo resistor with tunable resistance. The second transistor operates in the weak inversion region.

Abstract: A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.

Abstract: A two-step switching method of circuit switch can be used in a charge pump circuit of a phase locked loop circuit. In the method, a first type switch and a second type switch which have the same sizes and are opposite in type, are provided. The first type switch and second type switch continuously receive an input current, and the input current is kept at a low current state in a first stage before the first type switch and the second type switch are turned on. In a second stage, the first type switch and the second type switch are turned on, the input current is gradually adjusted to a target current state, and the input current of the target current state is gradually supplied to an external circuit. The present method can reduce noise generated by the external circuit, reduce power loss, and offset charge injection.

Abstract: A method of using machine learning algorithms in analyzing laboratory test results of body fluid to detect microbes in the body fluid includes using a body fluid detection module for analytic measurements in body fluid of a person to create biological samples; sending the biological samples of a plurality of persons and corresponding microbes infection statuses to perform machine learning algorithms to establish a microbes in body fluid prediction model; and sending data obtained from the body fluid detection of a patient for testing to the microbes in body fluid prediction model for operation and analysis in order to determine whether the microbes is present in body fluid.

Abstract: A charge pump circuit and a phase-locked loop (PLL) system using the same are provided. The charge pump circuit includes an upper current source, a lower current source and a plurality of switches. The switches are turned on or off by an error signal to increase or decrease the control voltage of the voltage-controlled oscillator (VCO) and further control the frequency of the output signal of the VCO. When the reference frequency signal matches with the divided frequency signal from the VCO, the upper current source and the lower current source are bypassed to decrease the voltage across the MOSFET, thereby minimizes the influence of the leakage current on the control voltage of VCO. In this way, the output jitter can be reduced due to smaller magnitude of peak-to-peak voltage on the control voltage of VCO in the PLL system caused by the leakage current of the MOSFET.

Abstract: A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.

Abstract: A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.

Abstract: A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.

Abstract: A lithium battery control circuit and a lithium battery charger are provided. The lithium battery charger includes the lithium battery control circuit. The lithium battery control circuit includes a smooth transition circuit and an off-time control circuit. The smooth transition circuit generates a first voltage according to a sense current signal and a feedback signal, and generates a second voltage according to a mode signal. The smooth transition circuit compares the first voltage with the second voltage to generate a reset signal. The off-time control circuit converts the feedback signal to generate a first current by a voltage-to-current mechanism, and generates a set signal by using the first current and a duty ratio signal. The invention may prevent a surge current and an oscillation phenomenon by the smooth transition circuit. A switching frequency and a ripple size of an output current are controlled by the off-time control circuit.

Abstract: A cochlear implant device comprises a receiver, a processing device, a first electrode and a second electrode. The receiver is configured to receive outside voice signal. The processing device is coupled to the receiver, configured to receive and transfer the voice signal to an electrical stimulation signal. The first electrode connects to the processing device, disposed on stapes footplate ligament or oval window. The second electrode connects to the processing device, disposed on round window. Wherein the electrical stimulation signal is applied to stapes footplate ligament, oval window or round window to stimulate acoustic nerve through the first electrode or the second electrode.

Abstract: A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.

Abstract: A pseudo resistor with tunable resistance including a first transistor and a second transistor is provided. The first transistor has a first terminal, a second terminal and a control terminal. The first terminal of the first transistor serves as a first terminal of the pseudo resistor. The control terminal of the first transistor receives a control voltage. The first transistor is controlled by the control voltage, such that the first transistor operates in a weak inversion region. The second transistor has a first terminal, a second terminal and a control terminal. The first terminal of the second transistor is coupled to the second terminal of the first transistor. The second terminal of the second transistor and the control terminal of the second transistor are coupled to each other to serve as a second terminal of the pseudo resistor with tunable resistance. The second transistor operates in the weak inversion region.