Patents by Inventor Chung-Ching Chen
Chung-Ching Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9424902Abstract: A memory controller is connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit. The memory controller includes: a processing unit, configured to receive a system address generated by the accessing unit; and a mapping unit, located in the processing unit, configured to convert the system address to a memory address and transmitting the memory address to the DDR DRAM. When a burst length of the DDR DRAM is L and L=2x (where L and x are positive integers), an (x+1)th bit of the memory address from a least significant bit (LSB) is included in a bank group address of the memory address.Type: GrantFiled: March 28, 2014Date of Patent: August 23, 2016Assignee: MStar Semiconductor, Inc.Inventors: Chung-Ching Chen, Chen-Nan Lin, Yung Chang
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Patent number: 9378800Abstract: The invention is directed to a memory controller and an associated signal generating method. By appropriately arranging a sequence according to which command signals are generated and expanding a latching interval of a part of address signals, not only the memory controller is enabled to control the DDR memory modules in a functional manner to further overcome issues of conventionally small latching intervals, but also system stability and access performance are reinforced as the memory access clock speed continue to increase.Type: GrantFiled: April 9, 2014Date of Patent: June 28, 2016Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Zong-Han Wu, Chen-Nan Lin, Chung-Ching Chen, Hsin-Cheng Lai
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Patent number: 9355744Abstract: A dynamic memory signal phase tracking method is provided. The method, applied to a memory controller that accesses a memory module, includes: issuing a memory access command and an access request to an arbiter to request for an access right of the memory module; when the access right is obtained, forwarding the memory access command to the memory module and asserting a flag signal; during a period of asserting the flag signal, sequentially using a plurality of candidate delay phases to adjust a memory signal for latching test data from the memory module, determining a delay phase according to latching results corresponding to the candidate delay phases, and recording the determined delay phases; updating an optimal delay phase according to the determined delay phase; and accessing the memory module according to the updated optimal delay phase.Type: GrantFiled: July 1, 2014Date of Patent: May 31, 2016Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Yung Chang, Chen-Nan Lin, Chung-Ching Chen
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Publication number: 20160124648Abstract: An apparatus for managing a memory having a plurality of command/address pins is provided. The apparatus includes a command generating module and a control module. The command generating module generates a set of target commands. The set of target commands include a plurality of command groups. Each of the command groups corresponds to at least one command/address pin of the plurality of command/address pins. It is known that the memory accesses the set of target commands from the plurality of command/address pins at a target time point. The control module controls the command groups to have different transition times prior to the target time points when the command groups are transmitted on the plurality of command/address pins.Type: ApplicationFiled: October 6, 2015Publication date: May 5, 2016Inventors: Yung Chang, Chen-Nan Lin, Chung-Ching Chen
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Publication number: 20150062138Abstract: A timing controller for a panel display system includes: an image signal receiver that receives an image signal; an overdrive circuit that receives and converts the image signal from the image signal receiver according to successive first frame data and second frame data in the image signal; an image signal transmitter that receives the converted image signal from the overdrive circuit and transmits the same to a display panel; a memory; and a memory interface unit. In a normal read/write period, the memory interface unit receives the first frame data from the overdrive circuit and stores the same in the memory, and fetches the first frame data from the memory when the overdrive circuit receives the second frame data in the image signal and transmits the same to the overdrive circuit. The memory interface unit further obtains sampling results to generate a preferred delay phase.Type: ApplicationFiled: September 4, 2014Publication date: March 5, 2015Inventors: Qi-Xin Chang, Jian-Kao Chen, Yung Chang, Chen-Nan Lin, Chung-Ching Chen
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Publication number: 20150006807Abstract: A dynamic memory signal phase tracking method is provided. The method, applied to a memory controller that accesses a memory module, includes: issuing a memory access command and an access request to an arbiter to request for an access right of the memory module; when the access right is obtained, forwarding the memory access command to the memory module and asserting a flag signal; during a period of asserting the flag signal, sequentially using a plurality of candidate delay phases to adjust a memory signal for latching test data from the memory module, determining a delay phase according to latching results corresponding to the candidate delay phases, and recording the determined delay phases; updating an optimal delay phase according to the determined delay phase; and accessing the memory module according to the updated optimal delay phase.Type: ApplicationFiled: July 1, 2014Publication date: January 1, 2015Inventors: Yung Chang, Chen-Nan Lin, Chung-Ching Chen
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Publication number: 20140379976Abstract: A memory controller and an associated signal generating method are provided. A generating sequence of commands is properly arranged to enlarge latching intervals of an address signal and a bank signal for stable access of a DDR memory module.Type: ApplicationFiled: June 23, 2014Publication date: December 25, 2014Inventors: Zong-Han Wu, Chen-Nan Lin, Chung-Ching Chen, Yung Chang
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Publication number: 20140325465Abstract: A chip with flexible pad sequence manipulation is provided. The chip can be a memory controller, and includes a hub unit. The hub unit, formed by a gate array, is placed in a hub region predetermined during placing and routing procedures, and is capable of supporting re-placing and re-routing for changing interior interconnections and a pad sequence of the chip.Type: ApplicationFiled: April 24, 2014Publication date: October 30, 2014Applicant: MStar Semiconductor, Inc.Inventors: Hsin-Cheng Lai, Yung Chang, Chen-Nan Lin, Chung-Ching Chen, Chen-Hsing Lo, Shang-Yi Chen, Cheng-Hsun Liu
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Publication number: 20140325137Abstract: The invention is directed to a memory controller and an associated signal generating method. By appropriately arranging a sequence according to which command signals are generated and expanding a latching interval of a part of address signals, not only the memory controller is enabled to control the DDR memory modules in a functional manner to further overcome issues of conventionally small latching intervals, but also system stability and access performance are reinforced as the memory access clock speed continue to increase.Type: ApplicationFiled: April 9, 2014Publication date: October 30, 2014Applicant: MStar Semiconductor, Inc.Inventors: Zong-Han Wu, Chen-Nan Lin, Chung-Ching Chen, Hsin-Cheng Lai
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Publication number: 20140293726Abstract: A memory controller is connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit. The memory controller includes: a processing unit, configured to receive a system address generated by the accessing unit; and a mapping unit, located in the processing unit, configured to convert the system address to a memory address and transmitting the memory address to the DDR DRAM. When a burst length of the DDR DRAM is L and L=2x (where L and x are positive integers), an (x+1)th bit of the memory address from a least significant bit (LSB) is included in a bank group address of the memory address.Type: ApplicationFiled: March 28, 2014Publication date: October 2, 2014Applicant: MStar Semiconductor, Inc.Inventors: Chung-Ching Chen, Chen-Nan Lin, Yung Chang
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Patent number: 8850248Abstract: A multi-core electronic system for accessing a data storage device includes a plurality of processors, a data transmission interface and a rate adjustment module. The processors respectively provide a bandwidth requirement, and communicate with the data storage device via the shared data transmission interface. The rate adjustment module receives the bandwidth requirements, and determines a transmission rate of the data transmission interface according to the bandwidth requirements.Type: GrantFiled: July 26, 2011Date of Patent: September 30, 2014Assignee: MStar Semiconductor, Inc.Inventors: Ping-Cheng Hou, Cheng-Yu Lu, Chieh-Wen Shih, Jen-Shi Wu, Chung-Ching Chen
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Patent number: 8782332Abstract: A DRAM controller including a judging module, a determination module, and a transmission module is provided. The judging module judges an address content difference between a first command and a third command. The determination module determines a plurality of buffering address contents, associated with at least one second command, according to the address content difference. The transmission module then sequentially transmits the first command, the at least one second command, and the third command to the DRAM.Type: GrantFiled: June 24, 2011Date of Patent: July 15, 2014Assignee: MStar Semiconductor, Inc.Inventors: Chung-Ching Chen, Hsian-Feng Liu, Yu-Lin Chen
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Patent number: 8773932Abstract: A built-in self-test circuit (BIST) applied to a high speed I/O port is provided. The BIST circuit includes a detecting unit, a flag unit and a selecting unit. The detecting unit has a first input terminal for receiving a serial output signal, a second input terminal for receiving a serial enable signal, and an output terminal for generating a detection signal. The flag unit receives the detection signal and generates a flag signal. The selecting unit receives the serial output signal, the serial enable signal and the flag signal. When a reset signal is at a first level, the selecting unit transmits the serial output signal and the serial enable signal to the I/O port. When the reset signal is at a second level, the serial output signal and the serial enable signal possesses a predetermined relationship.Type: GrantFiled: February 1, 2013Date of Patent: July 8, 2014Assignee: MStar Semiconductor, Inc.Inventors: Yu-Lin Chen, Hsian-Feng Liu, Chung-Ching Chen
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Patent number: 8635569Abstract: A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.Type: GrantFiled: November 17, 2010Date of Patent: January 21, 2014Assignee: MStar Semiconductor, Inc.Inventors: Sterling Smith, Hsian-Feng Liu, Eer-Wen Tyan, Chun-Chia Chen, Ming-Chieh Yeh, Chung-Ching Chen, Yo-Lin Chen
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Patent number: 8478581Abstract: An embodiment provides (a) a method and system for representing natural languages in a common machine-readable form, including the thorough design of the lexicon and grammar, the resulting representation called interlingua, (b) a method and system for using a computer to convert a text of a natural language into and out of a coded text of said interlingua representation, including a programming framework which is independent of other languages, said system is called interlingua engine, and (c) a method and system of machine translation using said interlingua engine, said system called interlingua machine translation system. Alternative embodiments are described.Type: GrantFiled: January 25, 2010Date of Patent: July 2, 2013Inventor: Chung-ching Chen
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Patent number: 8405678Abstract: A display controller for displaying multiple windows and associated memory access method are provided. The display controller receives a first video source and a second video source for displaying multiple windows, and includes a line buffer, a deinterlacer, a scaler, and a memory interface unit. The line buffer buffers pixel data of a non-overlapped area of a main image associated with the first video source, and pixel data of a sub image associated with the second video source. The deinterlacer is coupled to the line buffer for selectively deinterlacing data in the line buffer. The scaler is coupled to the deinterlacer for selectively scaling data outputted from the deinterlacer. The memory interface unit is coupled to the line buffer for accessing an external memory.Type: GrantFiled: April 30, 2008Date of Patent: March 26, 2013Assignee: MSTAR Semiconductor, Inc.Inventors: Kun-Nan Cheng, Yuan-Chuan Hsu, Hung-Yi Lin, Chung-Ching Chen
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Publication number: 20120272080Abstract: A multi-core electronic system for accessing a data storage device includes a plurality of processors, a data transmission interface and a rate adjustment module. The processors respectively provide a bandwidth requirement, and communicate with the data storage device via the shared data transmission interface. The rate adjustment module receives the bandwidth requirements, and determines a transmission rate of the data transmission interface according to the bandwidth requirements.Type: ApplicationFiled: July 26, 2011Publication date: October 25, 2012Applicant: MSTAR SEMICONDUCTOR, INC.Inventors: Ping-Cheng Hou, Cheng-Yu Lu, Chieh-Wen Shih, Jen-Shi Wu, Chung-Ching Chen
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Publication number: 20120226852Abstract: A DRAM controller including a judging module, a determination module, and a transmission module is provided. The judging module judges an address content difference between a first command and a third command. The determination module determines a plurality of buffering address contents, asoociated with at least one second command, according to the address content difference. The transmission module then sequentially transmits the first command, the at least one second command, and the third command to the DRAM.Type: ApplicationFiled: June 24, 2011Publication date: September 6, 2012Applicant: MStar Semiconductor, Inc.Inventors: CHUNG-CHING CHEN, Hsian-Feng Liu, Yu-Lin Chen
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Publication number: 20110184718Abstract: An embodiment provides (a) a method and system for representing natural languages in a common machine-readable form, including the thorough design of the lexicon and grammar, the resulting representation called interlingua, (b) a method and system for using a computer to convert a text of a natural language into and out of a coded text of said interlingua representation, including a programming framework which is independent of other languages, said system is called interlingua engine, and (c) a method and system of machine translation using said interlingua engine, said system called interlingua machine translation system. Alternative embodiments are described.Type: ApplicationFiled: January 25, 2010Publication date: July 28, 2011Inventor: Chung-ching CHEN
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Publication number: 20110131354Abstract: A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.Type: ApplicationFiled: November 17, 2010Publication date: June 2, 2011Applicant: MSTAR SEMICONDUCTOR, INC.Inventors: Sterling Smith, Hsian-Feng Liu, Eer-Wen Tyan, Chun-Chia Chen, Ming-Chieh Yeh, Chung-Ching Chen, Yo-Lin Chen