Abstract: The present invention relates to a memory circuit integrated in each pixel of a display device includes a switching circuit and a memory unit. The switching circuit includes a first transistor having a gate configured to receive a switching control signal, a source and a drain electrically coupled to a liquid crystal capacitor of the pixel, and a second transistor having a gate configured to receive a switching control signal, a source electrically coupled to a storage capacitor of the pixel, and a drain electrically coupled to the liquid crystal capacitor. The memory unit is electrically coupled between the source of first transistor and the storage capacitor.

Abstract: A data driver for time-division multiplexing includes a first memory cell set having first memory cells, a second memory cell set having second memory cells, and a plurality of output lines. Each first memory cell is used for generating a first data signal in response to a first sampling control signal, and for outputting the first data signal in response to a first transmitting control signal. Each second memory cell is used for generating a second data signal in response to a second sampling control signal, and for outputting the second data signal in response to a second transmitting control signal. During a first line time period, the first sampling control signal is triggered while the second transmitting control signal is triggered. During a second line time period, the first transmitting control signal is triggered while the second sampling control signal is triggered.

Abstract: A method for driving an LCD device having a plurality of sets of gate lines is disclosed. The method includes sequentially enabling odd gate lines of a first set of gate lines in ascending order for writing first-polarity data into corresponding pixels based on a first common voltage during a first interval, sequentially enabling even gate lines of the first set of gate lines in ascending order for writing second-polarity data into corresponding pixels based on a second common voltage during a second interval, sequentially enabling even gate lines of a second set of gate lines in descending order for writing second-polarity data into corresponding pixels based on the second common voltage during a third interval, and sequentially enabling odd gate lines of the second set of gate lines in descending order for writing first-polarity data into corresponding pixels based on the first common voltage during a fourth interval.

Abstract: One aspect of the present invention relates to an inducing capacitance detector. In one embodiment, the inducing capacitance detector has an input terminal for receiving a supply voltage; a capacitive sensor array with a first output terminal and a second output terminal; an operational amplifier having an inventing input terminal electrically connected to the first output terminal of the capacitive sensor array, a non-inventing input terminal electrically connected to the second output terminal of the capacitive sensor array and the input terminal, and an output terminal for outputting an output signal, a feedback capacitor electrically connected between the inventing input terminal and the output terminal of the operational amplifier.

Abstract: A ring-based multi-push voltage-controlled oscillator (VCO) generates a multi-push output signal using a control voltage. The ring-based multi-push VCO includes a plurality of delay cells, a plurality of buffer amplifiers, and a bias unit. The delay cells connect each other in sequence to form a ring structure, and each delay cell connects with the respective buffer amplifier. The bias unit connects with the buffer amplifiers to output the multi-push output signal. The control voltage supplied to the delay cells is utilized to control the frequency of the multi-push output signal, and the ring structure formed by the delay cells is to multiply the frequency of the multi-push output signal to increase the frequency tuning range.

Abstract: An analog buffer having voltage compensation mechanism is disclosed for use in a source driving circuit of a liquid crystal display. The analog buffer includes a reference voltage generator, a plurality of capacitors, a plurality of switches, and a plurality of transistors. Each of the capacitors is utilized to store the gate-source voltage of the corresponding turn-on transistor for performing gate-source voltage compensation operation based on the reference voltages provided by the reference voltage generator. Each of the switches functions to control gate-source voltage compensation operation and is turned on/off in response to a corresponding control signal. The analog buffer is capable of compensating the gate-source voltages of turn-on transistors for generating an output voltage having an acceptable tiny offset with respect to an input voltage.

Abstract: A ring-based multi-push voltage-controlled oscillator (VCO) with the control voltage to generate the multi-push output signal is disclosed. The ring-based multi-push VCO includes a plurality of delay cells, a plurality of buffer amplifiers, and a bias unit. The delay cells connect each other in sequence to form a ring structure, and each delay cell connects with the respective buffer amplifier. The bias unit connects with the buffer amplifiers to output the multi-push output signal. The control voltage supplied to the delay cells is utilized to control the frequency of the multi-push output signal, and the ring structure formed by delay cells is to multiply the frequency tuning range.

Abstract: A shift register is used for outputting an output pulse at output end in response to a delay of an input pulse received at an input end. The shift register includes a controller, a pre-charging switch, a level shifting switch, and an output generator. The controller is used for generating a level switching signal. The pre-charging switch is used for conducting a first supply voltage to a level shifting node in response to the input pulse. The level shifting switch turns on in response to the level switching signal. The output generator is used for generating the output pulse at the output end, when the level shifting switch turns on.

Abstract: A level shift circuit for adjusting voltage level of an input signal includes a voltage dividing circuit coupled to a input terminal for outputting a first voltage signal in response to the input signal at the input terminal, and a buffer coupled to a first node for generating a second voltage signal by adjusting voltage level of the first voltage signal. The voltage dividing circuit includes a first load coupled between the first node and the first supply voltage, and a second load coupled between the input terminal and the first node.

Abstract: A source driver circuit includes several sampling-transmitting units each including a first sub-latch unit, a second sub-latch unit and a transmission channel set. In a first period, the first sub-latch unit samples first pixel data. In a second period, the second sub-latch unit samples second pixel data. The transmission channel set electrically couples the first sub-latch unit and the second sub-latch unit to a corresponding digital-to-analog converting unit. In the second period, the first sub-latch unit outputs the first pixel data to the corresponding digital-to-analog converting unit via the transmission channel set. In a third period, the second sub-latch unit outputs the second pixel data to the corresponding digital-to-analog converting unit via the transmission channel set.

Abstract: A touch panel includes a plurality of active pixel sensors arranged in an array to sense a touch event. Each sensor element includes a photo-sensing element coupled to a single amplifier. The sensor element is arranged to provide a sensing voltage indicative of a light level received by the photo-sensor in a sensing period. The sensing voltage is amplified by the amplifier into an output voltage in the sensing period. Following the sensing period, the output voltage and the sensing voltage are reset to a predetermined voltage level. Following the reset period, the photo-sensor as well as the amplifier is disabled for a period so that the sensing level is caused to drop below the predetermined voltage level.

Abstract: A clocked D-type Flip-Flop circuit has a transmission gate to admit an input data and to provide an intermediate output to a clock-controlled inverter based on the clock signals. The clock-controlled inverter is used as a latch for latching the output signal from the transmission gate and releases the latched signal by the same clock signals to an output inverter. The output of the output inverter is the Q terminal of the Flip-Flop circuit. Another output inverter is used to invert the signal from the Q terminal into a complementary output signal. In one of the embodiments of the present invention, another transmission gate is used to condition the complementary output signal.

Abstract: A switch set used in a bi-directional shift register circuit includes a plurality of switch devices. Each switch device is controlled by corresponding control signals to switch the direction of the input signal. One of the switch devices includes a first switch unit for transmitting a shift register signal from a previous shift register to a shift register according to a first control signal, a second switch unit for transmitting a shift register signal from a next shift register to the shift register according to a second control signal. The first and the second control signals have the same frequency as the clock signal of the shift register circuit.

Abstract: A pre-charge circuit includes a receiving module, an enabling module, and a reset module. The receiving module receives the received driving signal of the pre-charge circuit and outputs the receiving driving signal according to a control signal. The enabling module outputs a pre-charge signal when receiving the driving signal. The reset module is electrically coupled between the receiving module and the enabling module for receiving a reset signal to reset the pre-charge signal.

Abstract: A color sequential liquid crystal display and a pixel circuit thereof are provided. The pixel circuit includes a first and a second sampling switches, a first and a second voltage registers, a first and a second output switches, a liquid crystal (LC) capacitor, and a reset switch. The first voltage register is coupled to the first sampling and the first output switches to register a first sampling voltage during a first sub-frame, and output the first sampling voltage to the LC capacitor during a second sub-frame. The second voltage register is coupled to the second sampling and the second output switches to register a second sampling voltage during the second sub-frame, and output the second sampling voltage to the LC capacitor during the first sub-frame. The reset switch is coupled to the LC capacitor to transmit a reset voltage to the LC capacitor between the first and second sub-frame periods.

Abstract: A display apparatus and a data read-out controller thereof are provided. The display apparatus comprises a touch display module, a first data read-out controller, and a second data read-out controller. Each of the first and the second data read-out controllers comprises a first read-out switch, a second read-out switch, a first sampling unit, and a second sampling unit. According to the time division multiple output operated by the first sampling units, the first read-out switches, the second sampling units, and the second read-out switches of the first and the second data read-out controllers, the number of the output points and power loss can be reduced effectively.

Abstract: An LCD device and driving method thereof are disclosed. The LCD device includes a source driver, a controller, a voltage generator, a plurality of data lines, a plurality of pixels, and a plurality of demultiplexer modules. The controller provides two sets of control signals. The voltage generator provides an AC common voltage. Each demultiplexer module includes two demultiplexers. The first demultiplexer distributes data signals received from the source driver into a set of data lines based on the first set of control signals. The second demultiplexer distributes data signals received from the source driver into another set of data lines based on the second set of control signals. The driving method is utilized for writing a plurality of low-voltage data signals having different polarities into a plurality of pixels based on different common voltages during different intervals of a frame period.

Abstract: A data driver for time-division multiplexing includes a first memory cell set having first memory cells, a second memory cell set having second memory cells, and a plurality of output lines. Each first memory cell is used for generating a first data signal in response to a first sampling control signal, and for outputting the first data signal in response to a first transmitting control signal. Each second memory cell is used for generating a second data signal in response to a second sampling control signal, and for outputting the second data signal in response to a second transmitting control signal. During a first line time period, the first sampling control signal is triggered while the second transmitting control signal is triggered. During a second line time period, the first transmitting control signal is triggered while the second sampling control signal is triggered.

Abstract: A level shift circuit for adjusting voltage level of an input signal includes a voltage dividing circuit coupled to a input terminal for outputting a first voltage signal in response to the input signal at the input terminal, and a buffer coupled to a first node for generating a second voltage signal by adjusting voltage level of the first voltage signal. The voltage dividing circuit includes a first load coupled between the first node and the first supply voltage, and a second load coupled between the input terminal and the first node.

Abstract: A method for driving an LCD device having a plurality of sets of gate lines is disclosed. The method includes sequentially enabling odd gate lines of a first set of gate lines in ascending order for writing first-polarity data into corresponding pixels based on a first common voltage during a first interval, sequentially enabling even gate lines of the first set of gate lines in ascending order for writing second-polarity data into corresponding pixels based on a second common voltage during a second interval, sequentially enabling even gate lines of a second set of gate lines in descending order for writing second-polarity data into corresponding pixels based on the second common voltage during a third interval, and sequentially enabling odd gate lines of the second set of gate lines in descending order for writing first-polarity data into corresponding pixels based on the first common voltage during a fourth interval.