Patents by Inventor Chung-Chun Lee

Chung-Chun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200342833
    Abstract: A head mounted display system and a scene scanning method thereof are provided. In the method, one or more first scene images and a second scene image in a real environment are obtained. A preliminary virtual environment corresponding to the real environment from the first scene images is generated. The preliminary virtual environment is displayed with a perspective at a visual position. The virtual position is corresponding to a real position in the real environment where the second scene image is captured. The perspective to present the virtual environment is modified in response to a change of a pose of the user's head. Accordingly, a convenient way to scan the real environment is provided, and a complete virtual environment may be obtained.
    Type: Application
    Filed: October 9, 2019
    Publication date: October 29, 2020
    Applicant: XRSPACE CO., LTD.
    Inventors: Chung-Chih Tsai, Yu-Wen Lin, Chia-Chun Lee, Shi-Yuan Chiang
  • Publication number: 20200335477
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Application
    Filed: July 8, 2020
    Publication date: October 22, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
  • Patent number: 10756052
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Grant
    Filed: July 28, 2019
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
  • Patent number: 10665199
    Abstract: A liquid crystal display power saving method is disclosed. It includes steps of: (a) dividing output channels coupled to a panel into multiple sets and each set includes M output channels, M is a positive integer; (b) calculating an average of the (N?1)-th display line of the panel after charge sharing, N is a positive integer larger than 1; (c) determining whether each of M output channels consumes power when it transmits a data signal from the (N?1)-th display line to the N-th display line; (d) calculating total power consumption of transmitting the data signal from the (N?1)-th display line to the N-th display line under possible charge sharing methods among the M output channels; (e) selecting a lowest power consumption charge sharing method from the possible charge sharing methods; and (f) switching coupling relationships among the M output channels according to the lowest power consumption charge sharing method.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 26, 2020
    Assignee: Raydium Semiconductor Corporation
    Inventors: Shao-Chun Cheng, Chung-Sung Tsai, Chi-Te Lee, Yi-Ping Lee
  • Patent number: 10651429
    Abstract: An organic light-emitting diode (OLED) illuminating lamp sheet and a manufacturing method thereof are provided. The method for manufacturing an OLED illuminating lamp sheet includes: manufacturing an array substrate, the array substrate includes a first base and a first electrode formed on the first base; bonding an electrostatic film to a surface of the array substrate provided with the first electrode, forming a patterned electrostatic film by patterning the electrostatic film, and forming an organic film layer by taking the patterned electrostatic film as a mask; forming a second electrode and obtaining an OLED element; and encapsulating the OLED element and obtaining an OLED illuminating lamp sheet.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: May 12, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jie Sun, Chung Chun Lee, Chieh Hsing Chung
  • Publication number: 20200118833
    Abstract: A method includes: forming source/drain epitaxy structures over a semiconductor fin; forming a first ILD layer covering the source/drain epitaxy structures; forming a gate structure over the semiconductor fin and between the source/drain epitaxy structures; forming a capping layer over the gate structure; thinning the capping layer; forming a hard mask layer over the capping layer; forming a second ILD layer spanning the hard mask layer and the first ILD layer; forming, by using an etching operation, a contact hole passing through the first and second ILD layers to one of the source/drain epitaxy structures, the etching operation being performed such that the hard mask layer has a notched corner in the contact hole; filling the contact hole with a conductive material; and performing a CMP process on the conductive material until that the notched corner of the hard mask layer is removed.
    Type: Application
    Filed: December 13, 2019
    Publication date: April 16, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hao WU, Shen-Nan LEE, Chung-Wei HSU, Tsung-Ling TSAI, Teng-Chun TSAI
  • Publication number: 20200105538
    Abstract: A method includes forming a bottom layer of a multi-layer mask over a first gate structure extending across a fin; performing a chemical treatment to treat an upper portion of the bottom layer of the multi-layer mask, while leaving a lower portion of the bottom layer of the multi-layer mask untreated; forming a sacrificial layer over the bottom layer of the multi-layer mask; performing a polish process on the sacrificial layer, in which the treated upper portion of the bottom layer of the multi-layer mask has a slower removal rate in the polish process than that of the untreated lower portion of the bottom layer of the multi-layer mask; forming middle and top layers of the multi-layer mask; patterning the multi-layer mask; and etching an exposed portion of the first gate structure to break the first gate structure into a plurality of second gate structures.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Wei HSU, Yu-Chung SU, Chen-Hao WU, Shen-Nan LEE, Tsung-Ling TSAI, Teng-Chun TSAI
  • Publication number: 20200091617
    Abstract: In an embodiment, a downlight includes: a plurality of light emitting diodes (LEDs) disposed in a housing of the downlight, and a millimeter-wave radar. The millimeter-wave radar includes: an antenna disposed in the housing, a controller configured to: detect a presence of a human in a field-of-view of the millimeter-wave radar, determine a direction of movement of the detected human, and produce log data based on the direction of movement of the detected human, and a wireless module configured to transmit the log data to a wireless server.
    Type: Application
    Filed: September 13, 2018
    Publication date: March 19, 2020
    Inventors: Ho Chun Lee, Chung Hong Wong
  • Publication number: 20200083362
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes an AlN seed layer in direct contact with the substrate. The AlN seed layer includes an AlN first seed sublayer, and an AlN second seed sublayer, wherein a portion of the AlN seed layer closest to the substrate includes carbon dopants and has a different lattice structure from a substrate lattice structure. The semiconductor device includes a graded layer in direct contact with the AlN seed layer. The graded layer includes a first graded sublayer including AlGaN, a second graded sublayer including AlGaN, and a third graded sublayer including AlGaN. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 12, 2020
    Inventors: Chi-Ming CHEN, Po-Chun LIU, Chung-Yi YU, Chia-Shiung TSAI, Ru-Liang LEE
  • Publication number: 20200006230
    Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.
    Type: Application
    Filed: April 30, 2019
    Publication date: January 2, 2020
    Inventors: Tsung-Ling Tsai, Shen-Nan Lee, Mrunal A. Khaderbad, Chung-Wei Hsu, Chen-Hao Wu, Teng-Chun Tsai
  • Patent number: 10510555
    Abstract: A method for manufacturing a semiconductor device includes forming a gate electrode over a substrate; forming a hard mask over the gate electrode, in which the hard mask comprises a metal oxide; forming an interlayer dielectric (ILD) layer over the hard mask; forming a contact hole in the ILD layer, wherein the contact hole exposes a source/drain; filling the contact hole with a conductive material; and applying a chemical mechanical polish process to the ILD layer and the conductive material, wherein the chemical mechanical polish process stops at the hard mask, the chemical mechanical polish process uses a slurry containing a boric acid or its derivative, the chemical mechanical polish process has a first removal rate of the ILD layer and a second removal rate of the hard mask, and a first ratio of the first removal rate to the second removal rate is greater than about 5.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hao Wu, Shen-Nan Lee, Chung-Wei Hsu, Tsung-Ling Tsai, Teng-Chun Tsai
  • Patent number: 10510867
    Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor Chiuan Hsieh, Chung-Ting Ko, Ting-Gang Chen, Chien Chung Huang, Tai-Chun Huang, Tze-Liang Lee
  • Patent number: 10497574
    Abstract: A method includes forming a spin-on carbon (SOC) layer over a target structure; chemically treating an upper portion of the SOC layer; forming a sacrificial layer over the SOC layer; performing a chemical mechanical polish (CMP) process on the sacrificial layer until reaching the SOC layer, wherein the chemically treated upper portion of the SOC layer has a higher resistance to the CMP process than that of the sacrificial layer; forming a patterned photoresist layer over the SOC layer after the CMP process; and etching the target structure using the patterned photoresist layer as a mask.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Wei Hsu, Yu-Chung Su, Chen-Hao Wu, Shen-Nan Lee, Tsung-Ling Tsai, Teng-Chun Tsai
  • Publication number: 20190355694
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Application
    Filed: July 28, 2019
    Publication date: November 21, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
  • Patent number: 10483386
    Abstract: A semiconductor device includes a substrate, and a seed layer over the substrate, wherein the seed layer comprises carbon dopants. The semiconductor device further includes a channel layer over the seed layer, and an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. A method of making a transistor includes forming a seed layer over a substrate, and doping the seed layer, wherein doping the seed layer comprises introducing carbon dopants into the seed layer. The method further includes forming a channel layer over the seed layer, and forming an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 10366966
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer and a core material layer are sequentially formed on a first carrier. A portion of the core material layer is removed to form a core layer having a plurality of cavities. The first carrier, the dielectric layer, and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. The first carrier is removed from the dielectric layer. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
  • Patent number: 10367040
    Abstract: A display panel, which an also function as a touch input device, includes a substrate and at least one TFT on the substrate. Such a multi-function panel also includes a force sensor sensitive to pressure of touches on the panel. The force sensor includes a first conductive layer and a second conductive layer on the substrate.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: July 30, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chang-Ting Lin, Chung-Wen Lai, Kuan-Hsien Jiang, Chang-Chun Wan, Kuo-Sheng Lee
  • Publication number: 20190160628
    Abstract: A method is provided and includes: measuring a surface profile of a polishing pad; obtaining a reference profile of the polishing pad; comparing the surface profile of the polishing pad with the reference profile to generate a difference result; determining a conditioning parameter value according to the difference result; and conditioning the polishing pad using the conditioning parameter value.
    Type: Application
    Filed: September 25, 2018
    Publication date: May 30, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shen-Nan LEE, Te-Chien HOU, Teng-Chun TSAI, Chung-Wei HSU, Chen-Hao WU
  • Patent number: 10288494
    Abstract: A thermometer circuit configured to estimate a monitored temperature is disclosed. The circuit includes an adjustable resistor presenting a first resistance value that is temperature-independent and a second resistance value that is temperature-dependent, wherein a first current signal is conducted across the resistor when it presents the first resistance value and a second current signal is conducted across the resistor when it presents the second resistance value; a plurality of gated conductors coupled to the resistor; and a control circuit, coupled to the resistor and the plurality of gated conductors, and configured to selectively deactivate at least one of the plurality of gated conductors to compare the first and second current signals to estimate the monitored temperature.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Chia-Fu Lee, Yi-Chun Shih, Chung-Cheng Chou, Yu-Der Chih
  • Publication number: 20190140076
    Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Bor Chiuan Hsieh, Chung-Ting Ko, Ting-Gang Chen, Chien Chung Huang, Tai-Chun Huang, Tze-Liang Lee