Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: A neuromorphic memory system including neuromorphic memory arrays. The neuromorphic memory system includes a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell. The method includes generating a presynaptic LIF pulse on a presynaptic LIF line at time t1. An activating operation activates an access transistor coupled to the presynaptic LIF line in response to the presynaptic LIF pulse. The access transistor enables LIF current to pass through the resistive memory cell to a postsynaptic LIF line. An integrating operation integrates the LIF current at the postsynaptic LIF line over time. A comparing operation compares a LIF voltage at the postsynaptic LIF line to a threshold voltage. A generating operation generates a postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: A neuromorphic memory circuit including a memory cell with a programmable resistive memory element. A postsynaptic capacitor builds up a leaky integrate and fire (LIF) charge. An axon LIF pulse generator activates a LIF discharge path from the postsynaptic capacitor through the resistive memory element when the axon LIF pulse generator generates axon LIF pulses. A postsynaptic comparator compares the capacitor voltage to a threshold voltage and generates postsynaptic output pulses when the capacitor voltage passes the threshold voltage. The postsynaptic output pulses include a postsynaptic firing characteristic dependent on a frequency of the axon LIF pulses. A refractory circuit prevents the postsynaptic comparator from generating additional postsynaptic output pulses until a refractory time passes since a preceding postsynaptic output pulse. A training circuit adjusts the postsynaptic firing characteristic to match a target firing characteristic.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.

Abstract: A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction, depositing a phase change material over the p-n junction, and forming a second electrode over the phase change material.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: A system for communicating postsynaptic neuron states. The system includes a first neuromorphic core and a second neuromorphic core. The first neuromorphic core includes a first array of synaptic memory cells and postsynaptic neuron circuits. Each of the postsynaptic neuron circuits is coupled to a row of synaptic memory cells in the first array of synaptic memory cells. Each of the postsynaptic neuron circuits is configured to fire when voltage sensed from the row of synaptic memory cells exceeds a threshold. The second neuromorphic core includes a second array of synaptic memory cells. A neuron bus is configured to serially transmit indications of a postsynaptic neuron circuit fire from the first neuromorphic core to the second neuromorphic core.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.

Abstract: A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.

Abstract: A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.

Abstract: A neuromorphic memory system including neuromorphic memory arrays. Each neuromorphic memory array includes rows and columns of neuromorphic memory cells. A column of postsynaptic circuits is electrically coupled to postsynaptic spike timing dependent plasticity (STDP) lines. Each postsynaptic STDP line is coupled to a row of neuromorphic memory cells. A column of summing circuits is electrically coupled to postsynaptic leaky integrate and fire (LIF) lines. Each postsynaptic LIF line is coupled to the row of neuromorphic memory cells at a respective memory array. Each summing circuit provides a sum of signals from the postsynaptic LIF lines to a respective postsynaptic circuit.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.