Patents by Inventor Chung-Hao Chu
Chung-Hao Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200194430Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a substrate, a growth promoting region, a first gate stack, and a second gate stack. The substrate includes a first region and a second region. The growth promoting region is located in a surface of the substrate in the first region. The growth promoting region includes a first implantation species, and a surface of the substrate in the second region is free of the first implantation species. The first gate stack includes a first gate dielectric layer on the substrate in the first region. The second gate stack includes a second gate dielectric layer on the substrate in the second region.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Patent number: 10672873Abstract: Provided is a semiconductor device including a substrate having a first conductivity type, an isolation structure, a well region having the first conductivity type, a gate structure, and doped regions having a second conductivity type. The isolation structure is disposed in the substrate to form an active region of the substrate. The well region is disposed in the active region and surrounds sidewalls of the isolation structure to form a native region in the active region. The gate structure is disposed over the substrate in the native region. The doped regions are disposed respectively in the well region and the native region of the substrate at two sides of the gate structure. A method of fabricating the semiconductor device is also provided.Type: GrantFiled: May 15, 2018Date of Patent: June 2, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu
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Patent number: 10658478Abstract: A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer, a metal layer, and a semiconductor layer. The metal layer is disposed on the gate dielectric layer. The semiconductor layer is disposed on the gate dielectric layer. The metal layer surrounds the semiconductor layer.Type: GrantFiled: December 28, 2018Date of Patent: May 19, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Meng-Chang Ho, Chung-Hao Chu, Tz-Hau Guo
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Patent number: 10622351Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.Type: GrantFiled: November 26, 2018Date of Patent: April 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Publication number: 20190355817Abstract: Provided is a semiconductor device including a substrate having a first conductivity type, an isolation structure, a well region having the first conductivity type, a gate structure, and doped regions having a second conductivity type. The isolation structure is disposed in the substrate to form an active region of the substrate. The well region is disposed in the active region and surrounds sidewalls of the isolation structure to form a native region in the active region. The gate structure is disposed over the substrate in the native region. The doped regions are disposed respectively in the well region and the native region of the substrate at two sides of the gate structure. A method of fabricating the semiconductor device is also provided.Type: ApplicationFiled: May 15, 2018Publication date: November 21, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu
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Publication number: 20190157408Abstract: A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer, a metal layer, and a semiconductor layer. The metal layer is disposed on the gate dielectric layer. The semiconductor layer is disposed on the gate dielectric layer. The metal layer surrounds the semiconductor layer.Type: ApplicationFiled: December 28, 2018Publication date: May 23, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Meng-Chang Ho, Chung-Hao Chu, Tz-Hau Guo
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Patent number: 10290725Abstract: A bipolar junction transistor includes a semiconductor substrate, a fin structure, an epitaxial emitter, an epitaxial collector and a gate. The fin structure is disposed on the semiconductor substrate and has a base portion of a first conductivity type, a first recessed portion and a second recessed portion. The epitaxial emitter of a second conductivity type is disposed in the first recessed portion of the fin structure. The epitaxial collector of the second conductivity type is disposed in the second recessed portion of the fin structure. The gate is disposed on the base portion of the fin structure and isolated from the base portion of the fin structure.Type: GrantFiled: March 22, 2017Date of Patent: May 14, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Hao Chu, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang
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Publication number: 20190109132Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a gate stack, a first doped region, a second doped region, and a buried doped region. The first doped region has a first conductivity type and is located in the substrate at a first side of the gate stack. The second doped region has the first conductivity type and is located in the substrate at a second side of the gate stack. The buried doped region has the first conductivity type and is buried in the substrate, extended from the first doped region to the second doped region, and separated from the gate stack by a distance.Type: ApplicationFiled: November 26, 2018Publication date: April 11, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Publication number: 20190096881Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.Type: ApplicationFiled: November 26, 2018Publication date: March 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Publication number: 20190006480Abstract: A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer, a metal feature, and a semiconductor feature. The metal feature is disposed on the gate dielectric layer. The semiconductor feature is disposed on the gate dielectric layer. The metal feature and the semiconductor feature are stacked on the gate dielectric layer side by side.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Meng-Chang Ho, Chung-Hao Chu, Tz-Hau Guo
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Patent number: 10170571Abstract: A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer, a metal feature, and a semiconductor feature. The metal feature is disposed on the gate dielectric layer. The semiconductor feature is disposed on the gate dielectric layer. The metal feature and the semiconductor feature are stacked on the gate dielectric layer side by side.Type: GrantFiled: June 30, 2017Date of Patent: January 1, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Meng-Chang Ho, Chung-Hao Chu, Tz-Hau Guo
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Patent number: 10157916Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.Type: GrantFiled: April 10, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Publication number: 20180294261Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.Type: ApplicationFiled: April 10, 2017Publication date: October 11, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Publication number: 20180277666Abstract: A bipolar junction transistor includes a semiconductor substrate, a fin structure, an epitaxial emitter, an epitaxial collector and a gate. The fin structure is disposed on the semiconductor substrate and has a base portion of a first conductivity type, a first recessed portion and a second recessed portion. The epitaxial emitter of a second conductivity type is disposed in the first recessed portion of the fin structure. The epitaxial collector of the second conductivity type is disposed in the second recessed portion of the fin structure. The gate is disposed on the base portion of the fin structure and isolated from the base portion of the fin structure.Type: ApplicationFiled: March 22, 2017Publication date: September 27, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Hao Chu, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang