Abstract: A memory structure includes: first and second word lines; a high-k dielectric layer disposed on the first and second word lines; a channel layer disposed on the high-k dielectric layer and comprising a semiconductor material; first and second source electrodes electrically contacting the channel layer; a first drain electrode disposed on the channel layer between the first and second source electrodes; a memory cell electrically connected to the first drain electrode; and a bit line electrically connected to the memory cell.

Abstract: A display device includes a substrate, a first display element which is disposed on the substrate, and a plurality of diffraction patterns which are disposed on a path of light emitted from the first display element and arranged along a direction with a first period. when a width of a cross section of one of the plurality of diffraction patterns is defined as a first length, the first period and the first length satisfy Inequality (1): 0.4 ? d ? 1 / DP ? 1 ? 1 , ( 1 ) where DP1 is the first period, and d1 is the first length.

Abstract: Thermal stability of a transistor is improved in different ways. An interfacial layer between a source/drain electrode and a semiconductor layer is formed from a material having a higher bond dissociation energy than indium oxide. Alternatively, the interfacial layer is formed from a metal-doped oxide semiconductor material. As another option, a metal layer or a metal oxide layer is formed between the source/drain electrode and the interfacial layer.

Abstract: An unmanned aerial vehicle includes a body, a shaft base, an arm, and a clamping assembly. The shaft base is disposed outside the body. The arm is pivotally disposed on the shaft base and is movably close to the body or unfolded from the body. The clamping assembly is movably and pivotally disposed on the shaft base and surrounds a periphery of the shaft base. When the arm is close to the body, the arm is limited between the body and the clamping assembly. During an unfolding process of the arm, the clamping assembly is pushed by the arm to be pivotally rotated on the shaft base. When the arm is unfolded from the body, the clamping assembly clamps the arm along a radial direction of the arm by an elastic force.

Abstract: An active metal brazing substrate material and a method for producing the same are provided. The active metal brazing substrate material includes a ceramic substrate layer, a first brazing layer, a second brazing layer, and a conductive metal layer that are sequentially stacked. The first brazing layer includes a first metal composite material, which includes silver (Ag), copper (Cu), and a first active metal element. Based on a total weight of the first metal composite material being 100 parts by weight, a silver content is not less than 50 parts by weight. The second brazing layer includes a second metal composite material, which includes aluminum (Al), copper (Cu), and a second active metal element, but does not contain silver. Based on a total weight of the second metal composite material being 100 parts by weight, an aluminum content is not less than 40 parts by weight.

Abstract: A composite material including an optically transparent substrate; a thermochromic layer such as the one including a halide perovskite-based compound provided on the substrate; and a protective layer provided on the thermochromic layer; wherein the optically transparent substrate includes a wood-based material impregnated with a first polymer. A method for preparing the composite material is also addressed.

Abstract: An active metal brazing substrate material and a method for producing the same are provided. The active metal brazing substrate material includes a ceramic substrate layer, a first brazing layer, a second brazing layer, and a conductive metal layer that are sequentially stacked. The first brazing layer includes a first metal composite material, which includes silver (Ag), copper (Cu), and a first active metal element. Based on a total weight of the first metal composite material being 100 parts by weight, a silver content is not less than 50 parts by weight. The second brazing layer includes a second metal composite material. The second metal composite material includes a low melting point metal element (e.g., Sn), copper (Cu), and a second active metal element, but does not include silver. A melting point of the low melting metal element is between 130° C. and 350° C.

Abstract: Various embodiments herein relate to a Mixed Reality (MR) control platform to operate a semiconductor manufacturing tool in an MR environment and to display data associated with the semiconductor manufacturing tool. In son embodiments, the MR control platform comprises an MR control system and an MR headset. The MR control system can obtain sensor data representative of sensor output from a semiconductor manufacturing tool. The MR control system can determine operational information associated with the semiconductor manufacturing tool and based on the sensor data. The MR control system can cause the operational information to be transmitted to the MR headset. The MR headset can receive the operational information associated with the semiconductor manufacturing tool from the MR control system. The MR headset can cause content associated with the operational information and one or more control features to be rendered in an MR environment.

Abstract: A reduced interfacial defect density and low contact resistance can be provided for a thin film transistor by using a compositionally-modulated capping layer. A stack including a gate electrode, a gate dielectric layer, an active layer including a semiconducting metal oxide material, an in-process capping layer including a dielectric metal oxide material can be formed over a substrate. A dielectric material layer can be formed, and a source cavity and a drain cavity can be formed through the dielectric material layer. Exposed portions of the in-process capping layer can be converted into conductive material portions to provide a compositionally-modulated capping layer, which includes a first conductive capping material portion, the second conductive capping material portion, and a dielectric capping material portion.

Abstract: A radiative cooling apparatus including a layer of a material. The layer defines an exterior face. The material has a composition such that the layer is configured to reflect, at the exterior face, at least partly of the incoming electromagnetic radiation of at least some wavelengths in the solar spectrum. The layer is further configured to emit thermally-generated electromagnetic emission of at least some mid-infrared wavelengths out from the exterior face. Ceramics provided by embodiments of the invention could produce extra cooling effect without any electricity consumption, creating a prominent benefit to the energy saving of air conditioning systems of buildings.

Abstract: A warp scheduling method includes: storing multiple first warps issued to a streaming multiprocessor in an instruction buffer module; marking multiple second warps which are able to be scheduled in the first warps by a schedulable warp indication window, wherein the number of the marked second warps is the size of the schedulable warp indication window; sampling a load/store unit stall cycle in each time interval to obtain a load/store unit stall cycle proportion; comparing the load/store unit stall cycle proportion with a stall cycle threshold value, and adjusting the size of the schedulable warp indication window and determining the second warps according to the comparison result; and issuing the second warps from the instruction buffer module to a processing module for execution.

Abstract: A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.

Abstract: A computer-implemented method includes gathering data samples into a data set, correcting for imbalance in the data set to produce a corrected data set by applying active learning to the data set to increase a number of double barreled question data samples occurring in the data set, selecting an optimal machine learning model for the corrected data set, training the optimal machine learning model using the corrected data set, operating the optimal machine learning model on new data to produce a prediction result, and generating a visual representation of at least one prediction results.

Abstract: A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; a gate dielectric layer disposed over the gate electrode; source/drain electrodes disposed above the gate electrode; and an active layer disposed above the gate electrode. A protection layer is disposed between the TFT and the MRAM cell and electrically connects the MRAM cell to the TFT.

Abstract: A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.

Abstract: A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.

Abstract: A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.

Abstract: A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.

Abstract: A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.

Abstract: A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; a gate dielectric layer disposed over the gate electrode; source/drain electrodes disposed above the gate electrode; and an active layer disposed above the gate electrode. A protection layer is disposed between the TFT and the MRAM cell and electrically connects the MRAM cell to the TFT.