Abstract: A silicon photonics optical transceiver device includes a silicon photonics optical module and a heat conducting housing that accommodates the silicon photonic optical module therein. The heat conducting housing has an inner surface formed with a first heat dissipation portion that wraps around and is in contact with transmitter optical sub-assemblies of the silicon photonics optical module to realize thermal conduction, and a second heat dissipation portion that is in contact with a digital signal processor of the silicon photonics optical module to realize thermal conduction.

Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

Abstract: The present disclosure provides a conductive paste for a solar cell electrode, comprising a metal powder, a glass frit, a metal oxide, an organic binder and a solvent, wherein the metal oxide comprises at least one metal oxide selected from the group consisting of tungsten (W), antimony (Sb), nickel (Ni), copper (Cu), magnesium (Mg), calcium (Ca), ruthenium (Ru), molybdenum (Mo), and bismuth (Bi).

Abstract: A semiconductor device includes; a first transistor on a substrate and including a first gate electrode, a second transistor on the substrate and including a second gate electrode adjacent to the first gate electrode, an electrode structure including electrodes vertically stacked on the first and second transistors and including first and second pads adjacent to in the first direction, first and second landing pads between the substrate and the electrode structure connected respectively to the first and second landing pads, a first penetration electrode penetrating the electrode structure to connect the first landing pad and the first pad, a second penetration electrode penetrating the electrode structure to connect the second landing pad and the second pad, and lower interconnection lines between the first landing pad and the second landing pad and extending in a second direction substantially perpendicular to the first direction.

Abstract: A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; a gate dielectric layer disposed over the gate electrode; source/drain electrodes disposed above the gate electrode; and an active layer disposed above the gate electrode. A protection layer is disposed between the TFT and the MRAM cell and electrically connects the MRAM cell to the TFT.

Abstract: A method for training a speech-emotion recognition classifier under a continuous self-updating and re-trainable ASER machine learning model, wherein the training data is generated by: obtaining an utterance of a human speech source; processing the utterance in an emotion evaluation and rating process with normalization; extracting the features of the utterance; quantifying the feature attributes of the extracted features by labelling, tagging, and weighting the feature attributes, with their values assigned under measurable scales; and hashing the quantified feature attributes in a feature attribute hashing process to obtain hash values for creating a feature vector space.

Abstract: A memory structure, device, and method of making the same, the memory structure including a surrounding gate thin film transistor (TFT) and a memory cell stacked on the GAA transistor. The GAA transistor includes: a channel comprising a semiconductor material; a source electrode electrically connected to a first end of the channel; a drain electrode electrically connected to an opposing second end of the channel; a high-k dielectric layer surrounding the channel; and a gate electrode surrounding the high-k dielectric layer. The memory cell includes a first electrode that is electrically connected to the drain electrode.

Abstract: A compiler includes a front-end module, an optimization module, and a back-end module. The front-end module pre-processes a source code to generate an intermediate code. The optimization module optimizes the intermediate code. The back-end module translates the optimized intermediate code to generate a machine code. Optimization includes translating a branch instruction in the intermediate code into performing the following operations: establishing a post dominator tree for the branch instruction to find an immediate post dominator of the branch instruction as a reconverge point of a first path and a second path of the branch instruction; inserting a specific instruction at the front end of the reconverge point, so as to jumping to execute the instructions of the second path on the condition that once the specific instruction on the first path is executed.

Abstract: A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.

Abstract: An imprinting apparatus includes an imprinting platform having a first side and a second side opposite to each other, an imprinting roller disposed above the imprinting platform, a transfer module, and a film separation module. The transfer module includes a transfer film located between the imprinting roller and the imprinting platform and a fixed frame fixed beside the first side of the imprinting platform and a movable frame disposed on the second side of the imprinting platform that clamp opposite sides of the transfer film. The movable frame is adapted to move horizontally relative to the fixed frame to change a flatness of the transfer film. The film separation module is connected to the movable frame, and is adapted to drive the movable frame to be turned from a first position to a second position, such that a rounded corner is formed between the transfer film and the imprinting roller.

Abstract: A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.

Abstract: A locking taper abutment with angle comprises a first part, a second part and a third part. The first part is configured to be engaged in an opening of a dental implant. The second part is connected above the first part, the second part comprises a lower region, a middle region, and an upper region, the lower region is positioned in alveolar bone, the upper region is positioned in gingiva, an expansion region is arranged on an outer periphery of the upper region, and the middle region or the lower region of the second part is provided with a bend; therefore, the problem that keratinized gingiva on a certain side is insufficient can be effectively solved. The third part is connected with the upper region of the second part for connection to a prosthesis, the third part being provided with at least one facet.

Abstract: An image sensor includes a semiconductor substrate having a first surface and a second surface, a pixel element isolation film extending through an interior of the semiconductor substrate and defining a plurality of active pixels in the semiconductor substrate, and a dummy element isolation film extending through the interior of the semiconductor substrate and extending along at least one side of the active pixels in a plan view and defining a plurality of dummy pixels in the semiconductor substrate. The pixel element isolation film may have a first end that is substantially coplanar with the first surface and has a first width in a first direction parallel to the first surface, and the dummy element isolation film has a first end that is substantially coplanar with the first surface and has a second width that is greater than the first width of the pixel element isolation film.

Abstract: A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.

Abstract: A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.

Abstract: Provided is an artificial intelligence (AI)-based peer-to-peer (P2P) power trading method and apparatus that encourages a household with relatively great power consumption or a household with relatively small power consumption according to a power load pattern for each time period to participate in power trading by optimizing power consumption through AI-based P2P power trading in a cluster including a nanogrid.

Abstract: A device structure includes at least one selector device. Each selector device includes a vertical stack including, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode and located over a substrate, a gate dielectric layer contacting sidewalls of the bottom electrode, the metal oxide semiconductor channel layer, and the top electrode, and a gate electrode formed within the gate dielectric layer and having a top surface that is coplanar with a top surface of the top electrode. Each top electrode or each bottom electrode of the at least one selector device may be contacted by a respective nonvolatile memory element to provide a one-selector one-resistor memory cell.

Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.

Abstract: The measurement method includes operations of applying a first gate bias voltage to a gate terminal of a first transistor that is included in a radio frequency (RF) power amplifier during a direct current (DC) measurement period, wherein the first transistor operates in a linear operation mode during the DC measurement period; measuring a first drain-source voltage of the first transistor and a current flowing through the first transistor via a connection node during the DC measurement period; applying a second gate bias voltage and a drain bias voltage to a gate terminal and a drain terminal of a second transistor that is electrically connected to the first transistor via the connection node; and measuring a DC value of the second transistor via the connection node during the DC measurement period.

Abstract: A software emulation system for a gas delivery system of a substrate processing system includes an input/output bus and an emulator bus. An input/output bus adapter includes a switch configured to route data packets from a system controller for the substrate processing system to one of the input/output bus and the emulator bus. A gas delivery system emulator in communication with the emulator bus is configured to receive the data packets from the input/output bus adapter via the emulator bus and perform software-based emulation of a plurality of hardware components of the gas delivery system that are interconnected. The plurality of hardware components are modelled using one or more software models and include a gas source and at least one of a valve and a mass flow controller.