Abstract: A semiconductor read-only memory (ROM) and a method of fabricating the same are provided. The ROM device is structured in such a manner that allows the fabrication to include a fewer number of mask processes. This makes it more cost effective and allows a cycle time that is shorter than that of the prior art. Moreover, the particular structure of the ROM device makes punchthrough less likely to occur between any neighboring pairs of the buried bit lines when the ROM device is further scaled down. The ROM device is constructed on a semiconductor substrate which is partitioned into a peripheral region and a cell region. A plurality of STI structures are formed at predefined locations in both the peripheral region and the cell region. Immediately after this, a first ion-implantation process can be performed on the cell region to form a plurality of buried bit lines.

Abstract: A semiconductor read-only memory (ROM) and a method of fabricating the same are provided. The ROM device is structured in such a manner that allows the fabrication to include a fewer number of mask processes. This makes it more cost effective and allows a cycle time that is shorter than that of the prior art. Moreover, the particular structure of the ROM device makes punchthrough less likely to occur between any neighboring pairs of the buried bit lines when the ROM device is further scaled down. The ROM device is constructed on a semiconductor substrate which is partitioned into a peripheral region and a cell region. A plurality of STI structures are formed at predefined locations in both the peripheral region and the cell region. Immediately after this, a first ion-implantation process can be performed on the cell region to form a plurality of buried bit lines.

Abstract: The present invention discloses a method of forming a contact window on a substrate. The method in the present invention includes a step of forming a gate structure on said substrate having a gate oxide, a gate electrode on the gate oxide, and a gate electrode protection layer on the gate electrode, a step of forming a protection layer conforming with the substrate and the gate structure, and a step of forming a first insulation layer over the protection layer. The method further includes removing a portion of the first insulation layer and a portion of the protection layer for forming side wall spacers at side walls of the gate structure, performing a ion implantation to the substrate using the gate structure and the side wall spacers as a mask, and then forming a second insulation layer on the substrate, the side wall spacers, and the gate structure.