Abstract: A mask used to form contact holes of 90 nm, 65 nm, and beyond, and methods of forming the mask. The mask comprises a mask substrate and at least one pattern on the mask substrate. The pattern includes a square opening formed as the center of a square, four square holes formed at the corners of the square, and four anti-scattering bars formed around the square opening. Each of those bars is located between two square holes and in the middle of one edge of the square. A layer of opaque material is formed on the spacing between the square opening, the anti-scattering bar and the square hole.

Abstract: Utilizing contact printing as the second exposure within a double exposure attenuated phase shift mask (APSM) fabrication process is disclosed. The process defines the shift pattern within the attenuated layer of the APSM using a first exposure, such as electron beam (e-beam) writing. The attenuated layer may be MoSi, MoSiO, and so on. The process then defines the border pattern within the opaque layer of the APSM using a second exposure. The second exposure employs contact printing, utilizing a contact exposure mask. The contact printing process may align the contact exposure mask over the wafer on which the APSM is fabricated utilizing a camera and an image storage system storing an image of this wafer.

Abstract: Employing a tri-tone attenuated phase shift trim mask in the second exposure of a double exposure alternating phase shift mask (alt-PSM) process is disclosed. A semiconductor wafer is first exposed utilizing a dark field alt-PSM, and then secondly is exposed utilizing a tri-tone attenuated PSM. The tri-tone attenuated PSM may include a transparent substrate, such as quartz, an opaque layer, such as chrome, and an attenuated layer, such as 6% transparency molybdenum silicide (MoSi). The opaque layer has a pattern corresponding to polysilicon gates to be imprinted on the semiconductor wafer, to protect the polysilicon photoresist patterns. The attenuated layer includes assist features to protect forbidden pitch semi-isolated field polysilicon patterns and isolated field polysilicon patterns to be imprinted on the semiconductor wafer.

Abstract: A new transistor structure with thermal protection is provided. A type of the new transistor structure of the present invention includes a main depletion-mode NMOSFET and a control PMOSFET, with the drain terminal of the control PMOSFET connected to the gate terminal of the main NMOSFET and the gate terminal of the control PMOSFET connected to a thermal protection unit. The two-MOSFET structure as a whole emulates a normal NMOSFET. The source terminal of the control PMOSFET that's not connected to the gate terminal of the main NMOSFET acts as the gate terminal of the new transistor structure, and the drain and source terminals of the new transistor structure are the drain and source terminals of the main NMOSFET. The thermal protection unit prevents thermal failures of the MOSFETs of the new transistor structure by sensing heat, terminating current through and switching the two MOSFETs.

Abstract: A method and circuit for improving a quality of display on an LCD screen are disclosed. The method is to synchronize a vertical synchronization signal of a video signal supplied to an LCD system with an oscillation signal produced by a burst mode DC-to-AC inverter driving the lamps of the system in order to suppress interference noise appearing on an LCD screen. The circuit suggested includes mainly two semiconductor switches, impedance elements, and a diode to realize the synchronization function.

Abstract: A new transistor structure with thermal protection is provided. A type of the new transistor structure of the present invention includes a main depletion-mode NMOSFET and a control PMOSFET, with the drain terminal of the control PMOSFET connected to the gate terminal of the main NMOSFET and the gate terminal of the control PMOSFET connected to a thermal protection unit. The two-MOSFET structure as a whole emulates a normal NMOSFET. The source terminal of the control PMOSFET that's not connected to the gate terminal of the main NMOSFET acts as the gate terminal of the new transistor structure, and the drain and source terminals of the new transistor structure are the drain and source terminals of the main NMOSFET. The thermal protection unit prevents thermal failures of the MOSFETs of the new transistor structure by sensing heat, terminating current through and switching the two MOSFETs.

Abstract: A method of forming photomasks is described which provides good critical dimension control for critical pattern elements and provides good throughput and low defect levels for etching relatively large areas of opaque material. The pattern is first modified to form a frame around the pattern elements which require good critical dimension control. The opaque material, such as chrome, in this frame is then etched away using dry anisotropic etching. The dry anisotropic etching provides good critical dimension control. The remainder of the opaque material to be removed is then etched away using wet isotropic etching. The wet isotropic etching provides good defect control in this region of the mask and good throughput. This method provides good critical dimension control at the edges of the pattern elements, good throughput in mask fabrication, and good defect level control in removing the relatively large areas of opaque material which do not affect critical dimension control.

Abstract: The invention relates to fabricating a single-trench alternating phase shift mask (PSM). A chromium layer over a mask layer, which is itself over a quartz layer, of the PSM is patterned according to a semiconductor design. The mask layer and the quartz layer are dry etched through a photoresist layer that has been applied over the chromium layer and patterned according to an alternating PSM design. The dry etching initially forms single trenches of the PSM. The quartz layer is next wet etched through the mask layer to completely form the single trenches of the PSM, where the photoresist layer has first been removed. The mask layer is dry etched again, where the single trenches of the PSM are initially filled with filler material to protect the single trenches from the dry etching.

Abstract: A method of forming contact holes in either a positive radiation sensitive layer, such as positive photoresist, or a negative radiation sensitive layer, such as negative photoresist, using three exposures is described. The sum of the three exposure doses is equal to that required to expose the entire radiation sensitive layer. The allowable contact hole locations are at the intersection of a first array of parallel regularly spaced lines and a second array of parallel regularly spaced lines. The lines are exposed in two separate exposures. For the positive radiation sensitive layer the contact holes are partially exposed by these exposures. For the negative radiation sensitive layer the contact holes remain unexposed by these exposures. The third exposure uses a pattern mask to either fully expose the contact holes in the positive radiation sensitive layer or leave them unexposed in the negative radiation sensitive layer. The radiation sensitive layer is then developed and the contact holes are formed.

Abstract: A method for transferring a pattern from a mask to a substrate (or wafer), comprises dividing a mask generation data file into a plurality of segments. The segments include a main pattern area and a stitching area. Each stitching area contains a respective common pattern. An image of an illuminated portion of the main pattern area is formed. Connection ends of the segments in a substrate area (or wafer area) are illuminated with an illumination beam. An image of the illuminated portion of the main pattern area is formed, and a halftone gray level dosage distribution is produced in the substrate area (or wafer area) corresponding to the common pattern. The common patterns of adjacent segments substantially overlap in the substrate area (or wafer area).

Abstract: Fabricating a dual-trench alternating phase shift mask (PSM) is disclosed. A chromium layer over a mask layer, which is over a quartz layer, of the PSM is patterned according to a semiconductor design. The mask layer is dry etched according to deep trenches of a PSM design. The quartz layer is dry etched a first number of times through a first photoresist layer applied over the chromium layer and patterned according to the deep trenches of the PSM design by using backside ultraviolet exposure. The mask layer is dry etched again, according to shallow trenches of the PSM design. The quartz layer is dry etched a second number of times through a second photoresist layer applied over the chromium layer and patterned according to the shallow trenches of the PSM design by using backside ultraviolet exposure.

Abstract: A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.

Abstract: A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.

Abstract: A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.

Abstract: A new method in the design for an electronic power supply for suppressing signal interference in equipment of an electronic system due to ground current in a ground loop is provided. In a power supply comprising a transformer, a primary circuit, a secondary circuit, and ground conductors, the method is done by connecting the common signal references of secondary side to the ground conductors through a capacitor and an inductor connected in series. The added capacitor is to reject DC and low frequency noise and interference, and the added inductor is to reject high frequency noise and interference. Most noise and interference signals therefore cannot pass through the formed paths. As a result, the degree of signal interference problem is greatly reduced.

Abstract: Employing a tri-tone attenuated phase shift trim mask in the second exposure of a double exposure alternating phase shift mask (alt-PSM) process is disclosed. A semiconductor wafer is first exposed utilizing a dark field alt-PSM, and then secondly is exposed utilizing a tri-tone attenuated PSM. The tri-tone attenuated PSM may include a transparent substrate, such as quartz, an opaque layer, such as chrome, and an attenuated layer, such as 6% transparency molybdenum silicide (MoSi). The opaque layer has a pattern corresponding to polysilicon gates to be imprinted on the semiconductor wafer, to protect the polysilicon photoresist patterns. The attenuated layer includes assist features to protect forbidden pitch semi-isolated field polysilicon patterns and isolated field polysilicon patterns to be imprinted on the semiconductor wafer.

Abstract: A method for forming a photomask and pellicle suitable for use in photolithography with incident electromagnetic radiation in a wavelength range from above 250 nm to below 150 nm. The opaque regions of the photomask are formed directly within a transparent F-doped quartz layer by either gallium ion staining using a focused ion beam (FIB) or by deposition of carbon atoms within trenches formed in the transparent layer, said carbon atom deposition being a result of the interaction of a FIB with styrene molecules. An alignment boundary formed on the resulting mask allows a hard pellicle to be fit directly over it so as to avoid warping.

Abstract: A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.

Abstract: Utilizing contact printing as the second exposure within a double exposure attenuated phase shift mask (APSM) fabrication process is disclosed. The process defines the shift pattern within the attenuated layer of the APSM using a first exposure, such as electron beam (e-beam) writing. The attenuated layer may be MoSi, MoSiO, and so on. The process then defines the border pattern within the opaque layer of the APSM using a second exposure. The second exposure employs contact printing, utilizing a contact exposure mask. The contact printing process may align the contact exposure mask over the wafer on which the APSM is fabricated utilizing a camera and an image storage system storing an image of this wafer.

Abstract: The invention relates to fabricating a single-trench alternating phase shift mask (PSM). A chromium layer over a mask layer, which is itself over a quartz layer, of the PSM is patterned according to a semiconductor design. The mask layer and the quartz layer are dry etched through a photoresist layer that has been applied over the chromium layer and patterned according to an alternating PSM design. The dry etching initially forms single trenches of the PSM. The quartz layer is next wet etched through the mask layer to completely form the single trenches of the PSM, where the photoresist layer has first been removed. The mask layer is dry etched again, where the single trenches of the PSM are initially filled with filler material to protect the single trenches from the dry etching.