Abstract: A multi-sided cooling semiconductor package includes a first substrate, a second substrate, semiconductor chips disposed between the first substrate and the second substrate, and first metal preforms. The first substrate includes a upper metal layer, a lower metal layer, and a dielectric plate between the upper metal layer and the lower metal layer. The second substrate also includes a upper metal layer, a lower metal layer, and a dielectric plate between the upper metal layer and the lower metal layer. The first metal preforms are disposed between the first substrate and the semiconductor chips and between the second substrate and the semiconductor chips. A first part of the first metal preforms is in direct contact with the upper metal layer of the first substrate, and a second part of the first metal preforms is in direct contact with the lower metal layer of the second substrate.

Abstract: A direct cooling power semiconductor package includes a power package and a cooling structure. The power package includes at least a power device on a first surface of a substrate, and the cooling structure is disposed on a second surface of the substrate, wherein the second surface and the first surface are opposite to each other, and the cooling structure includes a housing covering the second surface to form a containing space, a cooling liquid fluid or gas filled in the containing space, and a plurality of semi-closed metal structures. The semi-closed metal structures are in direct contact with the second surface in the housing.

Abstract: A multi-sided cooling semiconductor package includes a first substrate, a second substrate, semiconductor chips disposed between the first substrate and the second substrate, and first metal preforms. The first substrate includes a upper metal layer, a lower metal layer, and a dielectric plate between the upper metal layer and the lower metal layer. The second substrate also includes a upper metal layer, a lower metal layer, and a dielectric plate between the upper metal layer and the lower metal layer. The first metal preforms are disposed between the first substrate and the semiconductor chips and between the second substrate and the semiconductor chips. A first part of the first metal preforms is in direct contact with the upper metal layer of the first substrate, and a second part of the first metal preforms is in direct contact with the lower metal layer of the second substrate.

Abstract: A field-effect transistor (FET) structure for preventing from shorting is disclosed. The field-effect transistor (FET) structure is applying to a power discrete device, such as the MOSFET or IGBT. The field-effect transistor structure comprises a MOSFET chip and a metal clip. A silver layer (or silver string) is welded on the surface of the metal clip jointed with the source pad so that the silver paste may be not overflowed and permeated into the gate bus to achieve the effect of preventing from shorting.

Abstract: A field-effect transistor(FET) structure for preventing from shorting is disclosed. The field-effect transistor(FET) structure is applying to a power discrete device, such as the MOSFET or IGBT. The field-effect transistor structure comprises a MOSFET chip and a metal clip. A silver layer (or silver string) is welded on the surface of the metal clip jointed with the source pad so that the silver paste may be not overflowed and permeated into the gate bus to achieve the effect of preventing from shorting.

Abstract: A high heat-dissipation chip package structure for packaging the semiconductor chips is disclosed. A pre-attachment film is adhered on an upper surface of a heat-dissipation plate or a connection plate first and then it is packaged. After packaging, the pre-attachment film is torn off from the upper surface of the heat-dissipation plate or the connection plate. Finally, a metal layer is electroplated on the location of the upper surface of the heat-dissipation plate or the connection plate where the pre-attachment film is torn off so as to improve the fabricating and packaging quality of the semiconductor chips, reduce the cost of cleaning process, and improve the effects of heat dissipation and electrical conductivity.

Abstract: A high heat-dissipation chip package structure for packaging the semiconductor chips is disclosed. A pre-attachment film is adhered on an upper surface of a heat-dissipation plate or a connection plate first and then it is packaged. After packaging, the pre-attachment film is torn off from the upper surface of the heat-dissipation plate or the connection plate. Finally, a metal layer is electroplated on the location of the upper surface of the heat-dissipation plate or the connection plate where the pre-attachment film is torn off so as to improve the fabricating and packaging quality of the semiconductor chips, reduce the cost of cleaning process, and improve the effects of heat dissipation and electrical conductivity.

Abstract: A semiconductor transistor package structure is disclosed and is applicable for the transistors, such as IGBT or MOSFET. The structure is mainly used for electrically connecting with the chip and the lead frame or circuit board. Before soldering, a second layer is electroplated thereon to improve the drawbacks of the metal connecting wire easy to be oxidized and bad electrical connection. Besides saving the process time and enhancing yield rate, the life time of the transistors.

Abstract: The present invention is an improved packaging process of Intelligent Motion control Platform (IMP), which regards to the IMP improved process to change the manufacturing, assembling, and packaging process of printed circuit board (PCB) and Electromagnetic Compatibility (EMC). It is an improved manufacturing process to prevent from detecting the defects after IMP finishes packaging. After an IC chip is mounted to the PCB and then they are baked, it is tested first to be sure the IC chip and PCB are electrically connected, and then they are connected the EMS to be packaged together. By adding the above step, the packaged IMP can be sure to be operatable. Although there is an extra step added, the packaged IMP is promised to function. It can reach the goals of the present invention of increase the yield, decrease the number of defected products, and lower the cost.

Abstract: A pre molded can package includes a circuit board, a MEMS die, a pre mold cavity and a can. The MEMS dies are connected to the circuit board by conductive wires and the MEMS dies are separated by the pre mold cavities. A cap is connected to the top of each pre mold cavity to form MEMS die units. The MEMS die units are packed to as to reduce their volume. The manufacturing cost is reduced and the processes are simplified. The MEMS die units are able to be applied to the smaller and fine electronic devices.

Abstract: A molded can package includes a circuit board, a MEMS die and a can. The MEMS die is connected to the circuit board by a conductive wire. The can is mounted to the circuit board so as to isolate the MEMS die to form a MEMS die unit. A compound mold packs the MEMS die unit to prevent the MEMS die from being interfered and physically damage by electro-magnetic radiation and light so as to simplify the manufacturing processes and increase the production and reduce the cost.

Abstract: A chip package includes a conductive connection block connected to the conductive layer coated on the base and the two ends of the gold wire are respectively connected to the chip and the connection block. The connection block prevents lamination during packaging and ensures that the gold wire is firmly connected to the chip and the connection block.

Abstract: A lead frame includes a lead frame 11 made by a rolled single-layer of copper and has a lead portion and a chip support portion. The thickness of the lead portion is the same as that of the chip support portion. A heat dispensing plate made of Aluminum is connected to the chip portion and has a rough surface which is not connected with the lead frame. The lead frame is applied by Laser Diode To Package or metal-Oxide-Semiconductor Field Effect Transistor has high efficiency of heat dispensing and low manufacturing cost, and is suitable for different types of chips.

Abstract: A connection device includes a transistor, a lead frame, a first connection member and a second connection member. The signal is electronically connected between the transistor and the lead frame by the first and second connection members. The second connection member is located above the first connection member so as to increase the communication area for the signals and reduce the resistance between the transistor and the lead frame.

Abstract: A flip-chip block structure with block bumps comprises a die, a substrate, a first block bump, and a second block bump. The die comprises an active side and a backside, a first die pad and a second die pad are disposed on the active surface, and an electrode layer is disposed on the backside. The first die pad and the second die pad are connected to the pattern side of the substrate via the first block bump and the second block bump respectively. Besides, the first block bump and the second block bump are formed by a wedge bonding method, therefore, the block bumps are more easily formed into larger sizes, which enhance electrical performance and thermal dissipation performance of the flip-chip structure due to a lower contact resistance and a larger contact area between the die and the substrate.

Abstract: The present invention relates to a wire bonding structure, and more particularly to a manufacturing method for said wire bonding structure. The wire bonding structure comprises a die that connects with a lead via a bonding wire. At least one bond pad is positioned on an active surface of the die, and a gold bump is provided on the bond pad; furthermore, a ball bond can be positioned upon the gold bump. The bond pad and the gold bump can separate the ball bond and the die, which can avoid damaging the die during the bonding process.

Abstract: A flip-chip package structure comprises a carrier, a block bump, and a die. The carrier is a lead frame or substrate that comprises a lead pattern side, and an electrode pin is disposed on the lead pattern side. The die comprises an active side, and a bond pad is disposed on the active side. The block bump is bonded to the electrode pin; the bond pad of the die is attached on the carrier through the block bump, so that the die and the carrier joint together to form the flip chip package structure. Besides, the block bump is formed by the wedge bonding, and therefore in bumping size and shapes can easily form larger bump, which will increase the compactness between the die and the carrier.

Abstract: The present invention relates to a semiconductor device, and more particularly to a manufacturing method for said semiconductor device. The semiconductor device comprises a die that connects with a substrate or a lead frame via an adhesion layer, a metal layer, and/or a back metal layer. Furthermore, the adhesion layer can be made of aluminum, and the die can connect with the substrate or the lead frame by ultrasonic bonding technology, which can avoid heat damaging the die during the manufacturing process.

Abstract: The present invention relates to a flip-chip chip-scale package structure, and more particularly to a flip-chip chip-scale package structure with high thermal and electrical performance. The flip-chip chip-scale package structure comprising: a die, a substrate, and a metal ribbon. The die comprises a back-side metal and a plurality of bond pads. The die is bonded to the substrate by a plurality of bumps. The metal ribbon is bonded to the back-side metal by way of metal diffusion bonding. By using the package structure of the present invention, it provides high thermal and electrical performance for semiconductor devices.

Abstract: A flip-chip block structure with block bumps comprises a die, a substrate, a first block bump, and a second block bump. The die comprises an active side and a backside, a first die pad and a second die pad are disposed on the active surface, and an electrode layer is disposed on the backside. The first die pad and the second die pad are connected to the pattern side of the substrate via the first block bump and the second block bump respectively. Besides, the first block bump and the second block bump are formed by a wedge bonding method, therefore, the block bumps are more easily formed into larger sizes, which enhance electrical performance and thermal dissipation performance of the flip-chip structure due to a lower contact resistance and a larger contact area between the die and the substrate.