Abstract: The present invention relates to a wire bonding structure, and more particularly to a manufacturing method for said wire bonding structure. The wire bonding structure comprises a die that connects with a lead via a bonding wire. At least one bond pad is positioned on an active surface of the die, and a gold bump is provided on the bond pad; furthermore, a ball bond can be positioned upon the gold bump. The bond pad and the gold bump can separate the ball bond and the die, which can avoid damaging the die during the bonding process.

Abstract: The present invention provides the system design of the positioning analysis of a touch screen. It receives the signals from the wave sensor that employs the concept of the reflection of the light, sound, or supersonic, and the signals are calculated by the core logic circuit to obtain the position coordinate of an object. And then a display module is employed to show the moving path of the object in the manner of an image or line on a screen. The wave sensor may be implemented by a CMOS optical image sensor, infrared sensor, or supersonic sensor. The CMOS (Complementary metal oxide semiconductor) optical image sensor may additionally comprise fibers to transmit the optical wave to the CMOS sensor smoothly.

Abstract: A memory card comprising a leadframe having a plurality of contacts. Electrically connected to the leadframe is at least one semiconductor die. A body at least partially encapsulates the leadframe and includes opposed top and bottom surfaces, an opposed pair of longitudinal sides, and an opposed pair of lateral sides. The contacts of the leadframe are exposed in the bottom surface of the body and extend to one of the lateral sides thereof.

Abstract: A chip packaging structure without leadframe includes a bare chip having one surface provided with a plurality of contacts, and an adhesive and a fixing layer sequentially attached to the surface of the bare chip with the contacts, and a plurality of lead wires sandwiched between the adhesive and the fixing layer. Each of the lead wires has an inner end electrically connected to one of the contacts on the bare chip via an inner connecting window area provided on the adhesive layer corresponding to the contacts on the bare chip, and an outer end extended to one of multiple outer connecting window areas provided on the fixing layer to electrically connect to one of many external conducting bodies implanted in and exposed from the outer connecting window areas, such that no leadframe is needed to enable further reduced volume and decreased packaging cost of the whole chip packaging structure.

Abstract: A chip packaging structure without leadframe includes a bare chip having one surface provided with a plurality of contacts, and an adhesive and a fixing layer sequentially attached to the surface of the bare chip with the contacts, and a plurality of lead wires sandwiched between the adhesive and the fixing layer. Each of the lead wires has an inner end electrically connected to one of the contacts on the bare chip via an inner connecting window area provided on the adhesive layer corresponding to the contacts on the bare chip, and an outer end extended to one of multiple outer connecting window areas provided on the fixing layer to electrically connect to one of many external conducting bodies implanted in and exposed from the outer connecting window areas, such that no leadframe is needed to enable further reduced volume and decreased packaging cost of the whole chip packaging structure.

Abstract: A transistor structure includes at least one chip; a packaging insulating layer, a first adhesive layer, a conducting layer, and a second adhesive layer sequentially provided on one side of the chip having electrical contacts thereon, so that the conducting layer is bonded between the first and the second adhesive layer; and a leadframe bonded to an outer side of the second adhesive layer. The conducting layer may be a metal sheet, a metal film, or a type of conducting fiber. The leadframe is connected to the electrical contacts on the chip via lead wires, and at least one of the electrical contacts on the chip is connected to the conducting layer via a conductor, so that the conducting layer is able to isolate electrical noises and reduce electromagnetic interferences, improve rates of transmission and heat release, strengthen chip packaging structure, and serve as a common grounding circuit.

Abstract: A chip packaging structure without leadframe includes a bare chip having one surface provided with a plurality of contacts, and an adhesive and a fixing layer sequentially attached to the surface of the bare chip with the contacts, and a plurality of lead wires sandwiched between the adhesive and the fixing layer. Each of the lead wires has an inner end electrically connected to one of the contacts on the bare chip via an inner connecting window area provided on the adhesive layer corresponding to the contacts on the bare chip, and an outer end extended to one of multiple outer connecting window areas provided on the fixing layer to electrically connect to one of many external conducting bodies implanted in and exposed from the outer connecting window areas, such that no leadframe is needed to enable further reduced volume and decreased packaging cost of the whole chip packaging structure.

Abstract: A memory module with chip hold-down fixture includes a substrate, a plurality of sockets provided on one surface of the substrate and having conductive terminals provided on a bottom thereof for electrically connecting to circuits on the substrate, and a hold-down fixture assembled to a top of each socket. Each of the sockets is symmetrically provided at two opposite end walls with a retaining section each. The hold-down fixture is provided at two opposite end walls with a receiving section each corresponding to the retaining section on the socket, and at two lateral sides with a press portion each. The hold-down fixture is assembled to the top of the socket through engagement of the receiving sections with the retaining sections, so that the press portions are pressed against a chip positioned in the socket for the chip to contact with and electrically connect to the conductive terminals in the socket.

Abstract: A chip packaging structure adapted to reduce EMI includes a chip having contacts provided on one side thereof, and a leadframe having a plurality of leads arranged in a predetermined manner and provided at a bottom side with a conducting protrusion each for electrically connecting to external elements. The leadframe is fixedly attached to one side of the chip having the contacts provided thereon, and the leads are electrically connected at inner ends to the contacts via lead wires. An adhesive layer is applied to one side of the leadframe having the protrusions to thereby adhere a conducting layer to the leadframe with the protrusions downward extended through multiple through holes on the conducting layer; and at least one of the contacts on the chip is electrically connected to the conducting layer for the latter to serve as a ground or a power plane.

Abstract: A memory card with its memory chip replaceable as desires includes a circuit substrate disposed with control chip, chip contact and golden finger thereon, and a package externally to the circuit substrate to expose the golden finger from one side of the package; the package containing a slot to accommodate a socket for one end of the conductor in the socket to conduct through the chip contact of the circuit substrate for the memory chip to be placed into the socket as desired to conduct through the socket conductor, the chip contact and the golden finger for production cost reduction and replacement of memory chip as desired.

Abstract: A chip packaging structure adapted to reduce EMI includes a chip having contacts provided on one side thereof, and a leadframe having a plurality of leads arranged in a predetermined manner and provided at a bottom side with a conducting protrusion each for electrically connecting to external elements. The leadframe is fixedly attached to one side of the chip having the contacts provided thereon, and the leads are electrically connected at inner ends to the contacts via lead wires. An adhesive layer is applied to one side of the leadframe having the protrusions to thereby adhere a conducting layer to the leadframe with the protrusions downward extended through multiple through holes on the conducting layer; and at least one of the contacts on the chip is electrically connected to the conducting layer for the latter to serve as a ground or a power plane.

Abstract: An improved stack chip package comprising a lead frame, chip, plural leads and coating, among which: the lead frame is made of metal materials through impact extrusion forming two or four lines of rectangular plural pins comprising three lead segments making the pin -shaped; So install a chip on the first segment's inside surface, bond wires at the chip's bond pads and each segment will form an electrical connection, coat the part where the lead is jointed for the completion of sealing operation, i.e. the chip's upper and lower sides can be connected to another chip package by the contact of the first and second segments, and the chip package can be stacked freely besides reduced volume and strengthened data processing performance.

Abstract: A packaged chip lowering characteristic impedance comprises a chip, a lead wire frame, a plurality of metal layers, adhesive layers, lead wires, and a mold, being formed into TSOP LOC and thin-small-sized packaging types; from a specified site above or under each row of leads of the lead wire frame, metal layers are fixed respectively with adhesives layers to the lead wire frame; lead wires are connected respectively between electrode contacts of the chip and leads of the lead wire frame and a lead wire provided is connected between at least one lead and the metal layer, so the packaged chip using metal layers as a Ground or Power plane is formed; thus, electrical noises and EMI are lowered and a problem of poor transmission of signals is eliminated so that a stable transmission of signals and an efficient transmission speed may be further developed.

Abstract: A transistor structure includes at least one chip; a packaging insulating layer, a first adhesive layer, a conducting layer, and a second adhesive layer sequentially provided on one side of the chip having electrical contacts thereon, so that the conducting layer is bonded between the first and the second adhesive layer; and a leadframe bonded to an outer side of the second adhesive layer. The conducting layer may be a metal sheet, a metal film, or a type of conducting fiber. The leadframe is connected to the electrical contacts on the chip via lead wires, and at least one of the electrical contacts on the chip is connected to the conducting layer via a conductor, so that the conducting layer is able to isolate electrical noises and reduce electromagnetic interferences, improve rates of transmission and heat release, strengthen chip packaging structure, and serve as a common grounding circuit.

Abstract: An IC with stably mounted chip includes a chip, a leadframe, a bridge, and an encapsulating compound. The bridge is a flat arch made of a sheet material and includes a horizontal fixing section and a supporting section downward extended from each end of the fixing section. The chip is adhered to a bottom side of the fixing section of the bridge. The leadframe includes a plurality of leads arranged at two opposite sides of the chip. The encapsulating compound is applied to cover the chip, the bridge, and inner portions of the leads to complete a compact IC having a stably mounted chip and a reduced overall thickness. An additional chip may be adhered to a top of the bridge.

Abstract: The package of the present invention includes a chip located on a substrate with signal transferring device electrically connected between them. Solder balls connect the substrate and thus electrically connect the substrate to external circuits. Molding compound is covered to protect the chip and signal transferring means. The heat-slug is capped over the molding compound through a conductive glue. The entire area of the upper surface of the heat-slug is exposed to the ambient to improve the ability to spread heat.

Abstract: A semiconductor package comprising a die pad defining opposed top and bottom surfaces and a peripheral edge. Attached to the peripheral edge of the die pad is a plurality of support feet which extend downwardly relative to the bottom surface thereof. A plurality of leads extend at least partially about the peripheral edge of the die pad in spaced relation thereto. Attached to the top surface of the die pad is a semiconductor die which is electrically connected to at least one of the leads. A package body encapsulates the die pad, the support feet, the leads and the semiconductor die such that at least portions of the leads are exposed in the package body.

Abstract: A semiconductor package comprising a die pad defining opposed top and bottom surfaces and a peripheral edge. Attached to the peripheral edge of the die pad is a plurality of support feet which extend downwardly relative to the bottom surface thereof. A plurality of leads extend at least partially about the peripheral edge of the die pad in spaced relation thereto. Attached to the top surface of the die pad is a semiconductor die which is electrically connected to at least one of the leads. A package body encapsulates the die pad, the support feet, the leads and the semiconductor die such that at least portions of the leads are exposed in the package body.

Abstract: The package includes a chip located on a substrate with signal transferring device electrically connected between them. Solder balls connect the substrate and thus electrically connect the substrate to external circuits. Molding compound is covered to protect the chip and signal transferring means. The heat-slug is capped over the molding compound through a conductive glue. All area of the upper surface of the heat-slug is exposed to the ambient to improve the capability of spreading heat.

Abstract: The leadframe of the present invention comprises a supporting bar having the first terminals and the second terminals, wherein the first terminals are coupled to the separating portion of the leadframe and the second terminals are used to support the chip. A plurality of inner leads connected to the supporting bar. A plurality of external leads connected to the inner leads; Adhesive material, formed on the leadframe and used to attach the chip to the inner leads, wherein the area of adhesive material is smaller than that of said chip. A plurality of bonding wires is used to couple the chip to the leadframe. Finally, the chip is encapsulated with the molding compound to protect the chip and the bonding wires.