Patents by Inventor Chung-Hsun Lee

Chung-Hsun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190115067
    Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.
    Type: Application
    Filed: October 12, 2017
    Publication date: April 18, 2019
    Inventors: Chung-Hsun LEE, Hsien-Wen LIU
  • Patent number: 10262719
    Abstract: The present disclosure provides a dynamic random access memory (DRAM) and a method of operating the same. The DRAM includes a memory array, a refresh device and an access device. The refresh device is configured to perform a self-refresh operation on the memory array, wherein the self-refresh operation is interrupted in response to an access command. The access device is configured to access the memory array in response to the access command and the interruption of the self-refresh operation.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 16, 2019
    Assignee: Nanya Technology Corporation
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10236035
    Abstract: The present disclosure provides a dynamic random access memory (DRAM). The DRAM includes a refresh unit, an accessing device and a refresh device. The refresh unit has a plurality of memory rows. The accessing device is configured to access the memory rows. The refresh device is configured to refresh the refresh unit in a first manner in response to a first event, in which a quantity of accessed memory rows of the refresh unit is not greater than a threshold quantity. The refresh device is configured to refresh the refresh unit in a second manner in response to a second event, in which the quantity of accessed memory rows of the refresh unit is greater than the threshold quantity.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: March 19, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Publication number: 20190066760
    Abstract: The present disclosure provides a DRAM. The DRAM includes a memory array and a control device. The memory array has a plurality of word lines configured to control memory cells. The control device is configured to operate at least one word line of the word lines, derive an information on the operating of the at least word line, and cease maintaining data stored in the memory cells controlled by the at least one word line when the information satisfies a condition.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 28, 2019
    Inventors: Chung-Hsun LEE, Hsien-Wen LIU
  • Publication number: 20190066765
    Abstract: The present disclosure provides a DRAM including a first refresh unit, a second refresh unit, and a control device. The first refresh unit has a first quantity of valid data. The second refresh unit has a second quantity of valid data less than the first quantity of valid data. The control device is configured to determine that the first refresh unit has a greater quantity of valid data than the second refresh unit, move valid data of the second refresh unit into the first refresh unit, and cease refreshing the second refresh unit whose valid data was moved into the first refresh unit.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 28, 2019
    Inventors: Chung-Hsun LEE, Hsien-Wen LIU
  • Publication number: 20190065079
    Abstract: Present disclosure includes a system for preserving data in a volatile memory and a method thereof. The volatile memory comprises a plurality of refreshing units, and each of the refreshing units comprises a plurality of word lines for storing data. The system comprises an accessing unit. The accessing unit is configured to detect a row-hammer indication indicating a first word line is frequently accessed, wherein the accessing unit is configured to copy data stored in the first word line to a second word line when the row-hammer indication is detected on the first word line, wherein the data stored in the first and the second word lines are available to be selectively accessed.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 28, 2019
    Inventors: Chung-Hsun LEE, Hsien-Wen LIU
  • Publication number: 20190056874
    Abstract: Present disclosure relates to a system for preserving data in a volatile memory and a method thereof. The volatile memory comprises a plurality of word lines for storing data. The system comprises an accessing detector. The accessing detector is configured to detect a row-hammer indication indicating a first word line is frequently accessed, wherein the accessing detector is configured to copy data stored in the first word line to a second word line when the row-hammer indication is detected on the first word line, wherein the data stored in the first and the second word lines are available to be selectively accessed.
    Type: Application
    Filed: August 16, 2017
    Publication date: February 21, 2019
    Inventors: Chung-Hsun LEE, Hsien-Wen LIU
  • Patent number: 10141043
    Abstract: The present disclosure provides a dynamic random access memory (DRAM). The DRAM includes a plurality of banks, a power source and a control device. Each of the banks includes a plurality of subarrays. The control device derives information on a quantity of operated subarrays among the subarrays, and determines how much electrical energy to provide based on the information. The power source provides the resultant amount of electrical energy based on the determination from the control device.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: November 27, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10127967
    Abstract: The present disclosure provides a dynamic random access memory (DRAM). The DRAM includes a refresh unit and an accessing device. The refresh unit includes a target row on which a read/write (R/W) operation is requested to be performed. The accessing device is configured to perform the R/W operation on the target row while the refresh unit is being refreshed.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: November 13, 2018
    Assignee: Nanya Technology Corporation
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10049714
    Abstract: The present disclosure provides a DRAM. The DRAM includes a memory array of memory cells, a control device and a charge pump circuit. The control device derives an information associated with a command, and determine, based on the information, whether to provide an amount of electrical energy greater than, less than, or equal to an amount of electrical energy currently required. The charge pump circuit provides the memory array with the resultant amount of electrical energy based on the determination.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 14, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10019350
    Abstract: The present disclosure provides a method. The method includes copying a data stored in memory cells associated with a normal word line subject to a row hammer effect into memory cells associated with a hot word line before a condition is satisfied, wherein the condition includes an access frequency of the normal word line reaching a threshold frequency; accessing, based on a logical address, the normal word line before the condition is satisfied; accessing, based on the logical address, the hot word line associated with the copied data only if the condition is satisfied; and accessing the data no longer from the normal word line only if the condition is satisfied.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: July 10, 2018
    Assignee: Nanya Technology Corporation
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 8867272
    Abstract: A method of accessing a non-volatile memory is disclosed. Original bits of data are duplicated on a bit level to generate a plurality of duplicated bits corresponding to each original bit. At least one shielding bit is provided between the duplicated bits corresponding to different original bits. The duplicated bits and the at least one shielding bit are programmed to the non-volatile memory. The original bits are generated or determined according to the duplicated bits.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: October 21, 2014
    Assignee: Skymedi Corporation
    Inventors: Yi Chun Liu, Chung-hsun Lee, Ming Hung Chou
  • Publication number: 20140032813
    Abstract: A method of accessing a non-volatile memory is disclosed. Original bits of data are duplicated on a bit level to generate a plurality of duplicated bits corresponding to each original bit. At least one shielding bit is provided between the duplicated bits corresponding to different original bits. The duplicated bits and the at least one shielding bit are programmed to the non-volatile memory. The original bits are generated or determined according to the duplicated bits.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 30, 2014
    Applicant: SKYMEDI CORPORATION
    Inventors: Yi Chun Liu, Chung-hsun LEE, Ming Hung CHOU
  • Patent number: 8327218
    Abstract: A storage device and data processing method thereof is described. The invention provides different ECC for different memory pages. The storage device uses the long-bit ECC for easy interference page, and uses the short-bit ECC for hard interference page. Therefore, the accuracy of the data is maintained and the reading/writing speed is increased.
    Type: Grant
    Filed: June 5, 2010
    Date of Patent: December 4, 2012
    Assignee: A-Data Technology (Suzhou) Co., Ltd.
    Inventors: Chung-Hsun Lee, Tzu-Wei Fang
  • Publication number: 20110153961
    Abstract: The present invention discloses a storage device and an operation method thereof. The storage device includes a non-volatile memory for storing data, a control unit coupled to the non-volatile memory, a power supply unit coupled to an external power source and converting the external power source to a suitable voltage for the non-volatile memory and the control unit, and a power monitor unit for monitoring the external power source. When the external power source falls below a low voltage threshold of the non-volatile memory, a control signal is transmitted into the control unit so as to stop accessing the non-volatile memory. The non-volatile memory finishes the last processing procedure according to the last programming instruction sent by the control unit before the control signal for protecting the data stored in the non-volatile memory.
    Type: Application
    Filed: June 9, 2010
    Publication date: June 23, 2011
    Applicant: A-DATA TECHNOLOGY (SUZHOU) CO., LTD.
    Inventors: Hao-Po Chao, Chung-Hsun Lee
  • Publication number: 20110078541
    Abstract: A storage device and data processing method thereof is described. The invention provides different ECC for different memory pages. The storage device uses the long-bit ECC for easy interference page, and uses the short-bit ECC for hard interference page. Therefore, the accuracy of the data is maintained and the reading/writing speed is increased.
    Type: Application
    Filed: June 5, 2010
    Publication date: March 31, 2011
    Applicant: A-DATA TECHNOLOGY (SUZHOU) CO., LTD.
    Inventors: Chung-Hsun Lee, Tzu-Wei Fang