Patents by Inventor Chung-Hui Chen

Chung-Hui Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096804
    Abstract: A semiconductor device includes a first conductive line extending in a first direction on a front side of a semiconductor wafer, a first power rail extending in the first direction on a back side of the semiconductor wafer, and a first transistor including a first gate structure extending in a second direction perpendicular to the first direction, first and second active regions adjacent to the first gate structure, and a first channel region extending between the first and second active regions through the first gate structure. A first via is positioned between and electrically connects the first active region and the first conductive line, and a second via is positioned between and electrically connects the second active region and the first power rail.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventor: Chung-Hui CHEN
  • Publication number: 20240090053
    Abstract: In one example in accordance with the present disclosure, an electronic device is described. The electronic device includes a wireless controller. The wireless controller is to establish a first wireless connection between the electronic device and a peripheral device to receive a unique identifier for a second electronic device. The wireless controller is also to establish, based on the unique identifier for the second electronic device, a second wireless connection between the electronic device and the second electronic device. The electronic device includes a wireless transceiver to wirelessly transfer data to the second electronic device through the second wireless connection.
    Type: Application
    Filed: February 2, 2021
    Publication date: March 14, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Chung-Chun Chen, Chen-Hui Lin, Chih-Ming Huang, Ming-Shien Tsai
  • Publication number: 20240055468
    Abstract: A method of forming an inductor including forming a first redistribution structure on a substrate, forming a first conductive via over and electrically connected to the first redistribution structure, depositing a first magnetic material over a top surface and sidewalls of the first conductive via, coupling a first die and a second die to the first redistribution structure, encapsulating the first die, the second die, and the first conductive via in an encapsulant, and planarizing the encapsulant and the first magnetic material to expose the top surface of the first conductive via while a remaining portion of the first magnetic material remains on sidewalls of the first conductive via, where the first conductive via and the remaining portion of the first magnetic material provide an inductor.
    Type: Application
    Filed: January 23, 2023
    Publication date: February 15, 2024
    Inventors: Wei-Yu Chen, Chung-Hui Chen, Hao-Cheng Hou, Jung Wei Cheng, Tsung-Ding Wang, Chien-Hsun Lee, Shang-Yun Hou
  • Patent number: 11901289
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Te Chen, Chung-Hui Chen, Wei-Chih Chen, Chii-Ping Chen, Wen-Sheh Huang, Bi-Ling Lin, Sheng-Feng Liu
  • Patent number: 11901283
    Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Te Chen, Chung-Hui Chen, Wei Chih Chen
  • Publication number: 20240014124
    Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Te CHEN, Chung-Hui CHEN, Wei Chih CHEN
  • Patent number: 11842963
    Abstract: A semiconductor structure is disclosed, including a first conductive line and a first power rail and a first transistor structure arranged between the first conductive line and the first power rail. The first conductive line and the first power rail are separated from each other in a first direction. The first transistor structure includes a first active region coupled to the first conductive line by a first via; a second active region coupled to the first power rail by a second via; and a first gate structure interposed between the first active region and the second active region, and configured to receive a first control signal. The first transistor structure transmits a signal between the first conductive line and the first power rail in response to the first control signal.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chung-Hui Chen
  • Patent number: 11837535
    Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Xuan Huang, Hou-Yu Chen, Ching-Wei Tsai, Kuan-Lun Cheng, Chung-Hui Chen
  • Publication number: 20230387331
    Abstract: A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 30, 2023
    Inventor: Chung-Hui Chen
  • Publication number: 20230386993
    Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Yu-Xuan Huang, Hou-Yu Chen, Ching-Wei Tsai, Kuan-Lun Cheng, Chung-Hui Chen
  • Patent number: 11817452
    Abstract: A method disclosed includes the following operations as below: forming at least one capacitor between multiple interposing conductors and multiple gates; and forming multiple interposing connectors connected to the interposing conductors. One of the interposing conductors is interposed between two adjacent gates of the gates. In a plain view, the interposing connectors are separate from the gates.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Hui Chen, Hao-Chieh Chan, Wei-Chih Chen
  • Patent number: 11749759
    Abstract: A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chung-Hui Chen
  • Publication number: 20230275080
    Abstract: An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first transistor and a second transistor over the first side of the substrate, a first conductive pattern over the first side of the substrate, and a second conductive pattern under the second side of the substrate. The first conductive pattern electrically couples a first terminal of the first transistor to a second terminal of the second transistor. The second conductive pattern electrically couples the first terminal of the first transistor to the second terminal of the second transistor.
    Type: Application
    Filed: May 4, 2023
    Publication date: August 31, 2023
    Inventors: Chung-Hui CHEN, Tzu-Ching CHANG, Cheng-Hsiang HSIEH
  • Patent number: 11676957
    Abstract: An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first conductive pattern over the active region, and a second conductive pattern under the second side of the substrate. The active region includes a first portion and a second portion. The first conductive pattern is electrically coupled to the first portion and the second portion of the active region. The second conductive pattern is electrically coupled to the first portion and the second portion of the active region.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Hui Chen, Tzu-Ching Chang, Cheng-Hsiang Hsieh
  • Publication number: 20230170343
    Abstract: Methods and semiconductor devices are described herein which eliminate the use of additional masks. A first interconnect layer is formed. A first resistive layer is formed on top of the first interconnect layer. A dielectric layer is formed on top of the first resistive layer. A second resistive layer is formed on top of the dielectric layer.
    Type: Application
    Filed: January 12, 2023
    Publication date: June 1, 2023
    Inventors: Chung-Hui Chen, Wan-Te Chen, Cheng-Hsiang Hsieh, Chia-Tien Wu
  • Publication number: 20230154842
    Abstract: An integrated circuit includes a p-type active zone located in an n-type well, an n-type active zone located in a p-type well, an n-type pick-up region located in the n-type well, and a p-type pick-up region located in the p-type well. The integrated circuit also includes a first power rail and a second power rail extending in a first direction, and a first conductive segment and a second conductive segment extending in a second direction. The first power rail, the p-type active zone, the n-type active zone, and the second power rail are arranged along the second direction separating from each other. The first conductive segment connects the n-type pick-up region with the first power rail, and the second conductive segment connects the p-type pick-up region with the second power rail.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 18, 2023
    Inventors: Chung-Hui CHEN, Hao-Chieh CHAN
  • Publication number: 20230154991
    Abstract: A method of manufacturing a semiconductor structure includes forming an active region having a first portion which is doped. The method further includes forming a first silicide layer over and electrically coupled to the first portion of the active region. The method further includes forming a second silicide layer under and electrically coupled to the first portion of the active region. The method further includes forming a first metal-to-drain/source (MD) contact structure over and electrically coupled to the first silicide layer. The method further includes forming a first via-to-MD (VD) structure over and electrically coupled to the MD contact structure. The method further includes forming a buried via-to-source/drain (BVD) structure under and electrically coupled to the second silicide layer.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 18, 2023
    Inventors: Chung-Hui CHEN, Tung-Tsun CHEN, Jui-Cheng HUANG
  • Publication number: 20230062400
    Abstract: A method (of forming a semiconductor device) includes: forming an active area structure extending in a first direction; forming gate structures over the active area structure and extending in a second direction substantially perpendicular to the first direction; forming contact-source/drain (CSD) conductors over the active area structure, interleaved with corresponding ones of the gate structures, and extending in the second direction; and forming first conductive segments in a first layer of metallization (M_lst layer) over the active area structure and extending in the first direction, the first conductive segments including a first gate-signal-carrying (GSC) conductor which overlaps the active area structure.
    Type: Application
    Filed: November 8, 2022
    Publication date: March 2, 2023
    Inventors: Chung-Hui CHEN, Tzu Ching CHANG, Wan-Te CHEN
  • Patent number: D1003832
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: November 7, 2023
    Assignee: SCHNEIDER ELECTRIC IT CORPORATION
    Inventors: Chung-Hui Chen, Chien-An Lee, Ming Che Chan, Shen-Yuan Chien, Tannan Whidden Winter
  • Patent number: D1016738
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: March 5, 2024
    Assignee: SCHNEIDER ELECTRIC IT CORPORATION
    Inventors: Chung-Hui Chen, Chien-An Lee, Ming Che Chan, Shen-Yuan Chien, Tannan Whidden Winter