Patents by Inventor Chung-Hui Chen

Chung-Hui Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200373290
    Abstract: Methods and semiconductor devices are described herein which eliminate the use of additional masks. A first interconnect layer is formed. A first resistive layer is formed on top of the first interconnect layer. A dielectric layer is formed on top of the first resistive layer. A second resistive layer is formed on top of the dielectric layer.
    Type: Application
    Filed: January 16, 2020
    Publication date: November 26, 2020
    Inventors: Chung-Hui Chen, Wan-Te Chen, Cheng-Hsiang Hsieh, Chia-Tien Wu
  • Publication number: 20200328153
    Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Mirng-Ji Lii, Chung-Shi Liu, Chin-Yu Ku, Hung-Jui Kuo, Alexander Kalnitsky, Ming-Che Ho, Yi-Wen Wu, Ching-Hui Chen, Kuo-Chio Liu
  • Patent number: 10777260
    Abstract: An SRAM cell includes two inverters and three transistors. The first inverter includes a first end coupled to a first storage node and a second end coupled to a second storage node. The second inverter includes a first end coupled to the second storage node and a second end coupled to the first storage node. The first transistor includes a first end coupled to the first storage node, a second end and a control end. The second transistor includes a first end coupled to the second end of the first transistor, a second end coupled to a first bit line, and a control end. The third transistor includes a first end coupled between the second end of the first transistor and the first end of the second transistor, a second end, and a control end coupled to the first storage node.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zih-Yu Chiu, Hsin-Wen Chen, Ya-Nan Mou, Yuan-Hui Chen, Chung-Cheng Tsai
  • Patent number: 10777649
    Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsu-Hui Su, Chih-Ming Chen, Chia-Shiung Tsai, Chung-Yi Yu, Szu-Yu Wang
  • Publication number: 20200242294
    Abstract: A semiconductor device includes: an active area in a transistor layer; contact-source/drain (CSD) conductors in the transistor layer; gate conductors in the transistor layer, and interleaved with the CSD conductors; VG structures in the transistor layer, and over the active area; and a first gate-signal-carrying (GSC) conductor in an M_1st layer that is over the transistor layer, and that is over the active area; and wherein long axes correspondingly of the active area and the first GSC conductor extend substantially in a first direction; and long axes correspondingly of the CSD conductors and the gate conductors extend substantially in a second direction, the second direction being substantially perpendicular to the first direction.
    Type: Application
    Filed: January 13, 2020
    Publication date: July 30, 2020
    Inventors: Chung-Hui CHEN, Tzu Ching CHANG, Wan-Te CHEN
  • Patent number: 10720361
    Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang, Chung-Hui Chen
  • Patent number: 10700001
    Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mirng-Ji Lii, Chung-Shi Liu, Chin-Yu Ku, Hung-Jui Kuo, Alexander Kalnitsky, Ming-Che Ho, Yi-Wen Wu, Ching-Hui Chen, Kuo-Chio Liu
  • Publication number: 20200194326
    Abstract: A package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The conductive structures include elliptical columns. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is over the active surface of the die and the encapsulant. The redistribution structure is electrically connected to the die and the conductive structures.
    Type: Application
    Filed: February 24, 2020
    Publication date: June 18, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Publication number: 20200126901
    Abstract: An integrated circuit includes two parallel active zones extending in a first direction, an n-type pick-up region, and a p-type pick-up region. The two parallel active zones includes a p-type active zone located in an n-type well and an n-type active zone located in a p-type well. The n-type pick-up region is located in the n-type well and configured to have a first supply voltage. The p-type pick-up region is located in the p-type well and configured to have a second supply voltage, wherein the second supply voltage is lower than the first supply voltage. The n-type pick-up region and the p-type pick-up region are separated from each other along a direction that is different from the first direction.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 23, 2020
    Inventors: Chung-Hui CHEN, Hao-Chieh CHAN
  • Publication number: 20200126972
    Abstract: A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The gates are elongated in a second direction. The conductors are disposed between the active areas and elongated in the second direction. Each one of the conductors has an overlap with at least one corresponding gate of the gates to form at least one capacitor.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Hui CHEN, Hao-Chieh CHAN, Wei-Chih CHEN
  • Publication number: 20200119135
    Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 16, 2020
    Inventors: Hao-Chieh Chan, Chung-Hui Chen
  • Patent number: 10573573
    Abstract: A package includes a die, a plurality of first conductive structures, a plurality of second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. The first conductive structures include cylindrical columns and the second conductive structures include elliptical columns or conical frustums. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the active surface of the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: February 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Publication number: 20200058580
    Abstract: Semiconductor structures are provided. A semiconductor structure includes a substrate, a conductive plate of a first metal layer over the substrate, a first resistor material of a resistor layer over the conductive plate, a high-K material formed between the first resistor material and the conductive plate, a first conductive line of a second metal layer over the resistor layer, and a first via formed between the first conductive line and the first resistor material. The conductive plate, the first resistor material and the high-K material form a capacitor between the first and second metal layers. The first distance between the first resistor material and the conductive plate is less than the second distance between the first resistor material and the first conductive line.
    Type: Application
    Filed: January 3, 2019
    Publication date: February 20, 2020
    Inventors: Jiefeng Jeff LIN, Hsiao-Lan YANG, Chih-Yung LIN, Chung-Hui CHEN, Hao-Chieh CHAN
  • Publication number: 20200004130
    Abstract: A computing device and an input device are provided. Each of the computing device and the input device includes a control unit, a light source, a projection plate and a casing. The control unit, the light source and the projection plate are accommodated within the casing. The light source emits light beams. The projection plate includes a pattern. After the light beams pass through the projection plate, the light beams are projected outside the casing and an image corresponding to the pattern of the projection plate is formed on a projection surface that is located outside the casing. Since the projection plate is cheap and small, the fabricating cost of the computing device or the input device is reduced and the purpose of developing the computing device or the input device toward light weightiness, slimness and small size is achievable.
    Type: Application
    Filed: September 26, 2018
    Publication date: January 2, 2020
    Inventors: Wei-Chiang Huang, Chung-Yuan Chen, Chuan-Tai Hsiao, Ming-Hui Yeh
  • Patent number: 10522637
    Abstract: A semiconductor structure includes a first GAA transistor and a second GAA transistor. The first GAA transistor includes: a first diffusion region, a second diffusion region, and a first nanowire. The second GAA transistor includes: a third diffusion region, a fourth diffusion region, and a second nanowire. The first diffusion region, the second diffusion region, and the first nanowire are symmetrical with the third diffusion region, the fourth diffusion region, and the second nanowire respectively, the first GAA transistor is arranged to provide a first current to flow through the first nanowire, and the second GAA transistor is arranged to provide a second current to flow through the second nanowire.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chung-Hui Chen
  • Patent number: 10515947
    Abstract: A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The gates are elongated in a second direction. The conductors are disposed between the active areas and elongated in the second direction. Each one of the conductors has an overlap with at least one corresponding gate of the gates to form at least one capacitor.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Hui Chen, Hao-Chieh Chan, Wei-Chih Chen
  • Publication number: 20190386155
    Abstract: A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.
    Type: Application
    Filed: August 21, 2019
    Publication date: December 19, 2019
    Inventor: Chung-Hui CHEN
  • Patent number: 10509308
    Abstract: A computing device and an input device are provided. Each of the computing device and the input device includes a control unit, a light source, a projection plate and a casing. The control unit, the light source and the projection plate are accommodated within the casing. The light source emits light beams. The projection plate includes a pattern. After the light beams pass through the projection plate, the light beams are projected outside the casing and an image corresponding to the pattern of the projection plate is formed on a projection surface that is located outside the casing. Since the projection plate is cheap and small, the fabricating cost of the computing device or the input device is reduced and the purpose of developing the computing device or the input device toward light weightiness, slimness and small size is achievable.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 17, 2019
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Wei-Chiang Huang, Chung-Yuan Chen, Chuan-Tai Hsiao, Ming-Hui Yeh
  • Patent number: 10510826
    Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Chieh Chan, Chung-Hui Chen
  • Patent number: D883927
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: May 12, 2020
    Assignee: SCHNEIDER ELECTRIC IT CORPORATION
    Inventors: Ming Che Chan, Hsin-Hsiao Lin, Chung-Hui Chen