Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. The thermal conductive element at least partially overlaps the resistive element. In addition, the semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.

Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

Abstract: A circuit includes a thermoelectric structure and an energy device. The thermoelectric structure includes a wire and p-type and n-type regions positioned on a front side of a substrate, the wire configured to electrically couple the p-type region to the n-type region, a first via configured to thermally couple the p-type region to a first power structure on a back side of the substrate, and a second via configured to thermally couple the n-type region to a second power structure on the back side of the substrate. The energy device is electrically coupled to each of the first and second power structures.

Abstract: A method includes identifying at least a first mask or a second mask, fabricating, by the first mask, a first conductive line, fabricating, by the second mask, a second conductive line, and fabricating, by the first mask, a third conductive line if a dimension of the first conductive line is larger than a corresponding dimension of the second conductive line, or fabricating, by the second mask, the third conductive line if the dimension of the first conductive line is less than the corresponding dimension of the second conductive line A first circuit element is coupled to a second circuit element by at least the third conductive line, and the first circuit element is separated from the second circuit element by a predetermined distance.

Abstract: A semiconductor device including: a first S/D arrangement including a silicide-sandwiched portion of a corresponding active region having a silicide-sandwiched configuration, a first portion of a corresponding metal-to-drain/source (MD) contact structure, a first via-to-MD (VD) structure, and a first buried via-to-source/drain (BVD) structure; a gate structure over a channel portion of the corresponding active region; and a second S/D arrangement including a first doped portion of the corresponding active region; and at least one of the following: an upper contact arrangement including a first silicide layer over the first doped portion, a second portion of the corresponding MD contact structure; and a second VD structure; or a lower contact arrangement including a second silicide layer under the first doped portion, and a second BVD structure.

Abstract: A method of manufacturing a semiconductor device based on a dual-architecture-compatible design includes: forming transistor components of in a transistor (TR) layer; and performing one of fabricating additional components according to (A) a buried power rail (BPR) type of architecture or (B) a non-buried power rail (non-BPR) type of architecture. The step (A) includes, in corresponding sub-TR layers, forming various non-dummy sub-TR structures, and, in corresponding supra-TR layers, forming various dummy supra-TR structures which are corresponding first artifacts. The step (B) includes, in corresponding supra-TR layers, forming various non-dummy supra-TR structures and forming various dummy supra-TR structures which are corresponding second artifacts, the first and second artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the BPR type of architecture.

Abstract: An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first conductive pattern over the active region, and a second conductive pattern under the second side of the substrate. The active region includes a first portion and a second portion. The first conductive pattern is electrically coupled to the first portion and the second portion of the active region. The second conductive pattern is electrically coupled to the first portion and the second portion of the active region.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: An integrated circuit (IC) device includes a substrate, a first active region, first and second conductive patterns, and a first through via structure. The substrate has opposite first and second sides. The first active region is over the first side of the substrate. The first conductive pattern is over and electrically coupled to the first active region. The first through via structure extends from the second side, through the substrate, to the first side in electrical contact with the first active region. The second conductive pattern is under the second side of the substrate and electrically coupled to the first through via structure.

Abstract: A semiconductor structure is disclosed, including a first conductive line and a first power rail and a first transistor structure arranged between the first conductive line and the first power rail. The first conductive line and the first power rail are separated from each other in a first direction. The first transistor structure includes a first active region coupled to the first conductive line by a first via; a second active region coupled to the first power rail by a second via; and a first gate structure interposed between the first active region and the second active region, and configured to receive a first control signal. The first transistor structure transmits a signal between the first conductive line and the first power rail in response to the first control signal.

Abstract: A method of manufacturing conductive lines in a circuit is disclosed. The method includes grouping signal traces into a first set of signal traces and a second set of signal traces, fabricating, using a first mask, at least a first conductive line of a first signal trace of the first set of signal traces, and fabricating, using a second mask, at least a second conductive line of a second signal trace of the second set of signal traces. Each signal trace of the first set of signal traces has a first width. Each signal trace of the second set of signal traces has a second width different from the first width. The grouping is based on at least a current of at least a signal trace of the signal traces.

Abstract: A method disclosed includes the following operations as below: forming at least one capacitor between multiple interposing conductors and multiple gates; and forming multiple interposing connectors connected to the interposing conductors. One of the interposing conductors is interposed between two adjacent gates of the gates. In a plain view, the interposing connectors are separate from the gates.

Abstract: A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The gates are elongated in a second direction. The conductors are disposed between the active areas and elongated in the second direction. Each one of the conductors has an overlap with at least one corresponding gate of the gates to form at least one capacitor.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a substrate, a conductive plate of a first metal layer over the substrate, a first resistor material of a resistor layer over the conductive plate, a high-K material formed between the first resistor material and the conductive plate, a first conductive line of a second metal layer over the resistor layer, and a first via formed between the first conductive line and the first resistor material. The conductive plate, the first resistor material and the high-K material form a capacitor between the first and second metal layers. The first distance between the first resistor material and the conductive plate is less than the second distance between the first resistor material and the first conductive line.